关键词: Chisel语言, 异步FIFO, UVM, 逻辑综合

Abstract: Using Chisel, an agile hardware development language, the asynchronous first in first out (FIFO) commonly used in digital system design is designed, and language features of Chisel are used to improve the efficiency and quality of the design. The basic functional simulation verification of the designed asynchronous FIFO is carried out using the ChiselTest framework, the more complete functional simulation verification is carried out using the universal verification methodology (UVM), and the logic synthesis is carried out using the Quartus Ⅱ software. The synthesis results of asynchronous FIFOs designed with Chisel language and traditional hardware description language (HDL) are compared. The results show that the asynchronous FIFO designed with traditional HDL language consumes 50 combinational logic units, while the asynchronous FIFO designed with Chisel language consumes only 39 combinational logic units after synthesis.

Key words: Chisel language, asynchronous FIFO, UVM, logic synthesis