中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

导航

电子与封装 ›› 2022, Vol. 22 ›› Issue (4): 040501 . doi: 10.16257/j.cnki.1681-1070.2022.0410

• 产品与应用 • 上一篇    下一篇

基于SiP技术的网络测量探针芯片集成设计*

毛臻;张春平;潘福跃;顾林   

  1. 中科芯集成电路有限公司,江苏 无锡? 214072
  • 收稿日期:2021-07-14 出版日期:2022-04-25 发布日期:2021-11-23
  • 作者简介:毛  臻(1979—),男,江苏宜兴人,硕士,高级工程师,主要研究方向为微系统技术、嵌入式系统。

Probe Chip Design for Network Measurement Basedon SiP Technology

MAO Zhen, ZHANG Chunping, PAN Fuyue, GU Lin   

  1. China Key System &Integrated Circuit Co., Ltd., Wuxi 214072, China
  • Received:2021-07-14 Online:2022-04-25 Published:2021-11-23

摘要: 为了使主动网络测量探针国产化、小型化,通过分析目前CAIDA主推的最新主动探测终端工具群岛结构(Archipelago Measurement Infra-Structure,Ark)的硬件参数,并结合现有国产化裸芯片,设计了一种基于微系统技术的探针用主控系统级封装(System in Package,SiP)芯片。该探针主控SiP采用国产处理器搭配现场可编程门阵列(Field Programmable Gate Array,FGPA)的架构,集成双倍数据速率(Double Data Rate,DDR)内存颗粒和Flash等裸芯片,并选配了国产网络物理层芯片。设计完成的SiP芯片总体尺寸仅为30 mm′30 mm,最高主频为1 GHz,内存为2 GB,网口扩展为千兆。采用该探针芯片的系统从芯片选型到软件实现均采用全国产化设计,应用于国内网络测量场合时安全、保密性更高。

关键词: 主动网络测量, 国产化裸芯片, 探针芯片, 系统级封装

Abstract: In order to localize and miniaturize the active network measuring device, the hardware parameters of the latest active detection terminal tool archipelago measurement infra-structure (Ark) promoted by CAIDA is analyzed. Using domestic dies, a system in package (SiP) chip for probe based on microsystem technology is proposed, in which, domestic processor, field programmable gate array (FGPA), double data rate (DDR) memory, flash chips and Ethernet physical layer chip are integrated. All of the chips are intergrated in the size of 30 mm′30 mm. The frequency of the SiP is 1 GHz, the memory is 2 GB, and the network port speed is up to 1000 M. The chips and software design are fully domestic, with higher security and confidentiality when applied to domestic network measurement.

Key words: activenetworkmeasurement, domesticdie, probechip, systeminpackage

中图分类号: