关键词: 片上网络, 网络接口, 路由节点, 数据包

Abstract: Compared with the bus architecture, Network-on-Chip has the advantages of supporting parallel communication , great scalability, regular structure, reusability and so on. The network interface of which the data conversion and transmission efficiency affect the work efficiency of the whole Network-on-Chip, is between processor cores and routing nodes on Network-on-Chip. This paper focuses on the structure of Network-on-Chip and elaborates the design and verification of a network interface. The NoC system studied in this paper adopts the structure of 3×3 two-dimensional mesh. The DSP core adopts AMBA bus structure. The router adopts packet switching mode. In order to realize the data conversion and exchange between the dsp and router, the network interface is designed. In order to improve the transmission efficiency, the network interface design supports data batch transmission. The batch transmission does not need the DSP core. That saves the processor resources. After the RTL design of the network interface, the simulation is carried out to ensure the correctness of the network interface.

Key words: Network-on-Chip, Network interface, router, packet