一种面向RISC-V的检查点和回滚恢复容错方法*

doi:10.16257/j.cnki.1681-1070.2020.1002

电子与封装 ›› 2020, Vol. 20 ›› Issue (10): 100301 . doi: 10.16257/j.cnki.1681-1070.2020.1002

一种面向RISC-V的检查点和回滚恢复容错方法^*

常龙鑫;郭俊;洪广伟;虞致国;顾晓峰

Engineering Research Center of Ministry of Education for IoT Technology Applications, Department of Electronic Engineering, Jiangnan University, Wuxi 214122, China

收稿日期:2020-03-30 发布日期:2020-05-09
作者简介:常龙鑫（1997—），男，河南新乡人，硕士研究生，主要研究方向为集成电路设计。

A Checkpoint and Rollback Recovery FaultTolerance Method for RISC-V

CHANG Longxin, GUO Jun, HONG Guangwei, YU Zhiguo, GU Xiaofeng

Engineering Research Center of Ministry of Education for IoT TechnologyApplications, Department of Electronic Engineering, JiangnanUniversity, Wuxi 214122, China

Received:2020-03-30 Published:2020-05-09

摘要/Abstract

摘要： 随着特征尺寸的不断减小，CMOS集成电路更容易受到软错误的影响，可靠性设计已成为处理器设计中的重要考虑因素之一。基于对RISC-V特权级别、系统上下文、映射方法的研究，提出了一种面向RISC-V处理器的检查点和回滚恢复方法，并基于此实现了一种面向RISC-V的检查点和回滚恢复容软错误架构。在基于Artix-7开发板实现的e203 RISC-V内核中对该容错架构进行了仿真试验。试验结果表明，所提方法可以实现预期的容软错误功能，提高了RISC-V处理器的可靠性。

关键词: 软错误, 可靠性设计, RISC-V, 检查点和回滚恢复

Abstract: As the feature size continues to decrease, CMOS integrated circuits are more susceptible to soft errors. Reliability design has become one of the important considerations in processor design. Based on the research of RISC-V privilege level, system context, and mapping methods, a checkpoint and rollback recovery method for RISC-V processors is proposed. Based on this, a RISC-V oriented checkpoint and rollback recovery soft error tolerance architecture is implemented. Simulation experiment for the fault-tolerant architecture is performed in the e203 RISC-V core based on the Artix-7 development board. Experimental results show that the proposed method can achieve the expected function of soft error tolerance and improve the reliability of the RISC-V processor.

Key words: soft error, reliabilitydesign, RISC-V, checkpoint and rollback recovery

中图分类号:

TP302.8

常龙鑫;郭俊;洪广伟;虞致国;顾晓峰. 一种面向RISC-V的检查点和回滚恢复容错方法^*[J]. 电子与封装, 2020, 20(10): 100301 .

CHANG Longxin, GUO Jun, HONG Guangwei,YU Zhiguo, GU Xiaofeng. A Checkpoint and Rollback Recovery FaultTolerance Method for RISC-V[J]. Electronics & Packaging, 2020, 20(10): 100301 .

参考文献

[1] DODD P E, MASSENGILL L W. Basic mechanisms and modeling of single-event upset in digital microelectronics[J]. IEEE Transactions on Nuclear Science, 2003, 50(3):583-602.
[2] MUKHERJEE S. Architecture design for soft errors[M]. San Francisco: Margan Kaufmann, 2008:36-38.
[3] BAUMANN R C. Radiation-induced soft errors in advanced semiconductor technologies[J]. IEEE Transactions on Device & Materials Reliability, 2005, 5(3):305-316.
[4] GUPTA S, GALA N, MADHUSUDAN G S, et al. Shakti-F: A fault tolerant microprocessor architecture[C]. IEEE 24th Asian Test Symposium (ATS), Nov. 22-25, 2015, Mumbai, India. New York: IEEE, 2015:163-168.
[5] ICHINOMIYA Y, TANOUE S, AMAGASAKI M, et al. Improving the robustness of a softcore processor against seus by using tmr and partial reconfiguration[C]. 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, May. 2-4, 2010, Charlotte, North Carolina, USA. New York: IEEE, 2010:47-54.
[6] REIS G A, CHANG J, AUGUST D I. Automatic instruction-level software-only recovery[J]. IEEE Micro, 2007, 27(1):83-92.
[7] ASGHARI S A, TAHERI H, PEDRAM H, et al. Software-based control flow checking against transient faults in industrial environments[J]. IEEE Transactions on Industrial Informatics, 2013, 10(1): 481-490.
[8] ASANOVI? K, PATTERSON D A. Instruction sets should be free: The case for risc-v[R]. Berkeley: EECS Department, University of California, Berkeley, 2014.
[9] ASANOVI? K, AVIZIENIS R, BACHRACH J. The rocket chip generator[R]. Berkeley: EECS Department, University of California, Berkeley, 2016.
[10] CELIO C, DAVID A P, ASANOVI? K. The berkeley out-of-order machine (BOOM): An industry-competitive, synthesizable, parameterized RISC-V processor[R]. Berkeley: EECS Department, University of California, Berkeley, 2015.
[11] SI-RISC-V. 蜂鸟E203开源SoC简介[EB/OL]. [2020-03-13]. http://github.com/SI-RISCV/e200_opensource/blob/master/doc/蜂鸟E203开源SoC简介.pdf.
[12] RISC-V foundation. RISC-V software ecosystem overview[EB/OL]. [2020-03-13]. http://riscv.org/software-status.
[13] DE OLIVEIRA á B, RODRIGUES G S, KASTENSMIDT F L, et al. Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freertos applications[C]. 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI), Aug. 28- Sept. 1, 2017, Fortaleza, Brazil. New York: IEEE, 2017:84-89.
[14] PHAM H M, PILLEMENT S, PIESTRAK S J. Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor[J]. IEEE Transactions on Computers, 2013, 62(6):1179-1192.
[15] BOWEN N S, PRADHAN D K. Processor and memory-based checkpoint and rollback recovery[J]. Computer, 1993, 26(2):22-31.
[16] RISC-V foundation. The RISC-V instruction set manual volume 2: Privileged architecture[EB/OL]. [2020-03-13]. https://riscv.org/specifications/privileged-isa.
[17] TAMBARA L A, RECH P, CHIELLE E, et al. Analyzing the impact of radiation-induced failures in programmable SoCs[J]. IEEE Transactions on Nuclear Science, 2016, 63(4):2217-20224.
[18] SI-RISC-V. Hummingbird E203 opensource processor core[EB/OL]. [2020-03-13]. http://github.com/SI-RISCV/e200_opensource.
[19] YOUNG J W. A first order approximation to the optimum checkpoint interval[J]. Communications of the ACM, 1974, 17(9):530-531.
[20] 印杰, 江建慧. 复杂失效分布下的动态检查点设置[J]. 小型微型计算机系统, 2010(4):141-147.
[21] 袁宁,刘德峰. 动态检查点容错技术研究[C]//2006年第14届全国信息存储技术学术会议论文集. 武汉：中国计算机学会, 2006: 303-306.

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一种面向RISC-V的检查点和回滚恢复容错方法^*

A Checkpoint and Rollback Recovery FaultTolerance Method for RISC-V

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