中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2021, Vol. 21 ›› Issue (3): 030302 . doi: 10.16257/j.cnki.1681-1070.2021.0306

• 电路设计 • 上一篇    下一篇

一种PCIE交换电路设计与实现

林凡淼;刘 鑫;陆晓峰   

  1. 中科芯集成电路有限公司,江苏 无锡 214072
  • 收稿日期:2020-09-07 出版日期:2021-03-23 发布日期:2020-09-29
  • 作者简介:林凡淼(1988—),男,江苏无锡人,硕士,工程师,现从事IC应用测试及电路设计工作。

Design andImplementation of a PCIE Switching Circuit

LIN Fanmiao, LIU Xin, LU Xiaofeng   

  1. ChinaKey System & Integrated Circuit Co., Ltd., Wuxi 214072, China
  • Received:2020-09-07 Online:2021-03-23 Published:2020-09-29

摘要: 随着高速串行计算机扩展总线标准(PCIE)技术的成熟且应用场合越来越多,传统的“点对点”传输已不能满足不同设备之间高速数据传输的需求,因此有必要对PCIE数据交换技术进行研究。为了更加方便且高效地进行PCIE总线高速数据传输,也为了能将PCIE设备进行拓展,设计了一种以国产CPU为核心的PCIE交换电路,详细介绍了硬件设计方案及测试方法。在PCB板卡能正常工作的情况下逐渐增加ping包的量级(最高115200),稳定运行至少30 min后传输时间及丢包率小于10 ms和5×10-4,验证了设计的可行性与可靠性。

关键词: ?PCIE总线, PCIE交换电路, 高速数据传输, 丢包率

Abstract: With the maturity and more and more applications of peripheral component interconnect express (PCIE) technology, the traditional PCIE bus ‘point to point’ transmission cannot satisfy the needs of high-speed data transmission between different devices, so it is necessary to research PCIE data exchange technology. A PCIE switching circuit with domestic CPU as the core is designed in order to carry out high-speed data transmission of PCIE bus more conveniently and efficiently, and the hardware design scheme and test method are introduced in detail. Under the condition that the PCB can work normally, the magnitude of the ping package(up to 115200) is gradually increased, and the transmission time and packet loss rate are less than 10 ms and 5×10-4 after stable operation for at least 30 minutes. It verifies the feasibility and reliability of the design.

Key words: PCIEbus, PCIEswitchingcircuit, high-speeddatatransmission, packagelossrate

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