关键词: 板级扇出型封装, 芯片偏移量, 塑封制程, eSiFO

Abstract: Chip offset in the plastic sealing process has always been a huge challenge for panel-level fan-out package (FOPLP) technology. Based on the introduction of the existing FOPLP technology, the causes of chip offset in the plastic sealing process are analyzed, and the embedded silicon fan-out (eSiFO) technology of Huatian Technology is used for reference. Three feasible methods that can effectively reduce the chip offset in FOPLP are proposed, namely groove type plastic sealing structure method, penetration type plastic sealing structure method, and photoresist cofferdam type package structure method. The groove type plastic sealing structure method and penetration type plastic sealing structure method can reduce the chip offset in FOPLP by preparing the panel-level plastic sealing sample with groove type or penetration type structure, sticking the chip in the groove type or penetration type structure, and then combining with the vacuum film process. The photoresist cofferdam type package structure method uses photoresist to form a photoresist cofferdam structure on the carrier board, and sticks the chip in the photoresist cofferdam structure, in order to reduce the chip offset in FOPLP.

Key words: panel-level fan-out package, chip offset, plastic sealing process, eSiFO