关键词: Sigma-Delta调制器, CIFF, gain-boosting技术, DWA

Abstract: The design of a three-order three-bit quantized discrete-time Sigma-Delta modulator is described. Considering the power and area saving, a cascaded of integrators with feedforward (CIFF) structure is chosen for the modulator structure. The three-bit quantization of the modulator is realized by seven multi-bit comparators. In order to achieve high accuracy, gain-boosting technique is used to increase the gain of the operational amplifier in the integrator; at the same time, the data-weighted averaging (DWA) circuit is used to shape the noise introduced by the mismatch of the DAC capacitors at the input to increase the effective number of bits. The modulator is designed in 55 nm CMOS process, with a bandwidth of 16 kHz, an effective bit count of 19.10 bits, and a power consumption of 10.6 mW at a supply voltage of 3.3 V, a temperature of 27 ℃, and a typical tt process corner.

Key words: sigma-delta modulator,  CIFF, gain-boosting technique, DWA