关键词: QDR-Ⅱ+型同步SRAM, FPGA, 板级测试, CY7C1645KV18

Abstract: QDR-II+ synchronous SRAM is a new type of static random memory with high reliability, high speed and low power consumption, which is widely used in industrial Ethernet, Internet of Things, switches, servers and other network devices. QDR stands for Quad Date Rate. Compared with traditional DDR (Double Data Rate), the data input bus and output bus of QDR are independent, and the data can be operated on both rise and fall edges of the clock. QDR synchronous SRAMs designed for high data throughput. At the same time, due to the absence of complex dynamic refresh logic, power consumption of QDR devices is significantly reduced compared to DDR devices, making them more suitable for high-speed communication and high-speed network applications. However, due to the high operating frequency and the large storage depth， the board level performance evaluation and application of QDR-Ⅱ+synchronous SRAM have become an urgent problem to be solved. In this paper we choose CY7C1645KV18 from Cypress and design a board testing system mainly controlled by XC7K325T from Xilinx to evaluate the board level characteristics of QDR-Ⅱ+synchronous SRAM.

Key words: QDR-Ⅱ+ synchronous SRAM, FPGA; board-level test, CY7C1645KV18