关键词: 双路径电荷泵, 伪差分环形振荡器, 低抖动

Abstract: To address the inherent trade-off between loop bandwidth, stability, and phase noise in conventional phase-locked loops, a novel dual-path low-jitter phase-locked loops has been designed based on 40 nm CMOS technology. The core innovation lies in a self-biased integrator-amplifier dual-path charge pump that adaptively adjusts loop bandwidth, accelerating lock acquisition while reducing jitter. A pseudo-differential ring oscillator structure with a feedforward path further optimizes the oscillator's phase noise performance. Simulation results demonstrate that the phase-locked loops circuit locks to 960 MHz within 2.7 µs at a supply voltage of 2.5 V, achieving phase noise of -100.68 dBc/Hz@1 MHz and peak-to-peak jitter of 0.718 ps for the output clock. The circuit performance meets the receiver clock requirements for interface protocols such as USB 2.0.

Key words: dual-path charge pump, pseudo-differential ring oscillator, low jitter