中国电子学会电子制造与封装技术分会会刊

中国半导体行业协会封测分会会刊

无锡市集成电路学会会刊

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电子与封装

• 封装、组装与测试 •    下一篇

高像素线阵探测器与读出电路的低串扰互连研究

赵嘉铭,李良杰,曹嘉伟,周玉刚,陆海   

  1. 南京大学电子科学与工程学院第三代半导体与高能效器件重点实验室,南京  210023
  • 收稿日期:2026-02-28 修回日期:2026-03-30 出版日期:2026-04-14 发布日期:2026-04-14
  • 通讯作者: 周玉刚

Low-Crosstalk Interconnection Process for High-pixel Linear Detector Arrays and Readout Integrated Circuits

ZHAO Jiaming, LI Liangjie, CAO Jiawei, ZHOU Yugang, LU Hai   

  1. Jiangsu Key Laboratory of Advanced Semiconductors and High Energy Efficiency Devices, School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China
  • Received:2026-02-28 Revised:2026-03-30 Online:2026-04-14 Published:2026-04-14
  • Contact: Yugang Zhou

摘要: 在单光子探测成像领域中,为了获得更高的分辨率和更快的扫描探测速度,探测器正朝着大规模阵列化和高度集成化的方向发展。为满足碳化硅探测器在高可靠线阵应用中的需求,开发了适用于高像素线阵探测器与读出电路芯片的低串扰互连工艺。采用激光加工50 μm厚不锈钢硬掩模,并通过临时键合工艺在成品电路芯片焊盘表面沉积Ti/Ni/Au层,有效解决了芯片铝焊盘与In凸点浸润差导致键合强度低和虚焊问题。优化键合压力温度-时间曲线等工艺参数,结合半球吸嘴自适应调平解决键合不均匀引起的虚焊和短路。同时,用有限元仿真分析设计互连串扰,获得线阵规模达1×256,串扰信号幅值最低至输入信号幅值的0.1%以下。

关键词: 线阵探测器, 倒装互连, 低串扰

Abstract: To achieve higher resolution and faster scanning in single-photon detection imaging, detectors are evolving toward large-scale, highly integrated arrays. To meet the reliability requirements of silicon carbide detectors in linear array applications, a low-crosstalk interconnection process suitable for high-pixel linear detector arrays and readout integrated circuits was developed. A 50-μm-thick stainless steel hard mask fabricated by laser processing was employed, along with a Ti/Ni/Au layer deposited on the bonding pads of the finished circuit chip via a temporary bonding process, effectively mitigating the issues of low bonding strength and insufficient bonding caused by poor wettability between chip aluminum pads and In bumps. Process parameters such as bonding pressure and temperature–time profile were optimized, and adaptive leveling using a hemispherical nozzle was implemented to eliminate insufficient bonding and short circuits caused by non-uniform bonding. Additionally, finite element simulation was used to analyze and design the interconnection crosstalk, achieving a linear array scale of 1×256 with a crosstalk signal amplitude as low as below 0.1% of the input signal amplitude.

Key words: linear array detectors, flip-chip interconnection, low-crosstalk