关键词: 双核振荡器, F类振荡器, 三次谐波宽频电路, 品质因数, 脉冲敏感函数

Abstract: Oscillators are important clock generation modules in current communication systems. Advanced communication devices have an increasingly urgent demand for low phase noise (PN) oscillators. Three key technologies are adopted to optimize PN performance: Firstly, a dual-core cooperative oscillation structure is introduced to achieve a 3 dBc/Hz reduction in phase noise. Secondly, the Class-F oscillator structure is utilized to enhance the formation of the third harmonic at the drain to generate a pseudo-square wave voltage, reducing the noise factor. Additionally, the wideband third harmonic technology is employed to eliminate the need for additional drain switching capacitors. Finally, a second harmonic suppression circuit is used to effectively suppress the second harmonic up-conversion to PN. This dual-core Class-F₂₃ oscillator is designed based on the TSMC 28 nm CMOS process. Simulation results show that at a 0.9 V supply voltage and the tt process corner, the oscillation frequency ranges from 26.5 GHz to 30.8 GHz, with a power consumption of 28.6 mW and a frequency tuning range of 15%. At 28 GHz, the PN is -111.4 dBc/Hz at a 1 MHz offset and -133 dBc/Hz at a 10 MHz offset. The figure of merit (FoM) achieves 186 dBc/Hz at a 1 MHz offset. The dual-core Class-F₂₃ structure demonstrates great potential in harmonic suppression and noise optimization, and can be further applied to the development of terahertz band oscillators in the future.

Key words: dual-core oscillator, class-F oscillator, third harmonic wide-band circuit, FoM, impulse sensitivity function