关键词: CIC滤波器, 电压监控芯片, 电压数据校准

Abstract: This paper proposes a structural optimization method for the CIC decimation filter. By adopting the approach of segmenting the third-stage integrator and time-division multiplexing the subtractors, the proposed filter reduces power consumption by 18.4% and chip area by 17% compared with the standard recursive 3-stage cascaded CIC filter, thus achieving efficient utilization of hardware resources. Meanwhile, the design features configurable filter coefficients and supports 8 ADC precision modes with a passband frequency range of 26 Hz to 27 kHz, meeting the voltage measurement requirements of different precision levels. To address the issues of signal distortion and hardware errors in the voltage acquisition process, the filter integrates a real-time voltage calibration algorithm and a "0V" voltage calibration algorithm. These algorithms effectively suppress the dynamic errors caused by signal fluctuations and temperature drifts, and eliminate the systematic errors induced by chip process deviations and voltage asymmetry of multiplexer channels. Ultimately, the filter achieves the goals of anti-interference, high precision and high stability for voltage data acquisition of electric vehicle battery packs.

Key words: CIC filter, voltage monitoring chip, voltage data calibration