关键词: 硬件加速器, 现场可编程门阵列, 检测识别, 特征金字塔网络, 层间存储空间设计

Abstract: To improve the real-time performance ofYOLOv4for long-distance weak target detection, this paper proposes aYOLOv4forward inference accelerator targeting high-resolution image inputs and implements it on a Zynq FPGA heterogeneous platform. To address the memory bandwidth bottleneck caused by high-resolution feature maps, a dual-DRAM parallel memory access architecture is adopted. Combined with a pipelined task scheduling mechanism, the design enables concurrent access to weights and feature data, thereby improving memory bandwidth utilization. For the computation-intensive convolution layers, a loop tiling strategy together with an Im2col–GEMM computation mapping is employed to achieve efficient matching between convolution throughput and memory bandwidth. Furthermore, to accelerate the feature pyramid network (FPN), a dataflow restructuring method with preposed upsampling is proposed. The upsampling operation is implemented by repeated data reads controlled during the data-reordering stage, allowing the upsampling process to be performed implicitly in the dataflow without introducing additional computation units. This design avoids complex cross-row memory access patterns and decouples computation from memory access timing. Experimental results show that the optimizedYOLOv4model deployed on a Xilinx Zynq UltraScale+ MPSoCs platform achieves an equivalent computing performance of 179.4 Gop/s, with an inference frame rate of 13.6 FPS under 768×768 input resolution. Compared with the conventional sliding-window convolution implementation, the inference latency of individual network layers is reduced by 15.9%, the overall inference performance is improved by 67.2%, and the inference performance of the FPN module is improved by approximately 2×. Meanwhile, in long-range dim small-target scenarios, for targets whose image area accounts for approximately 10^-5 of the total image, the proposed method achieves improved detection performance while maintaining real-time capability, demonstrating the effectiveness of high-resolution input and structural optimization for weak target detection.

Key words: hardware accelerator, field programmable gate array, detection and recognition, feature pyramid network, inter-layer storage space design