关键词: 晶圆级三维集成, 设计方法与工具, 工艺, 热管理, 可靠性

Abstract: In 2010, the manufacturing platform based on Fin Field-Effect Transistors (FinFETs) was realized in the integrated circuits, thereby initiating the entry into the post-Moore era.  Under the subsequent path of space Scaling, the three major technical challenges were faced by it: physical limit constraints, rapid increase in economic costs, and performance growth bottlenecks. Therefore, the wafer-level three-dimensional integration technology was emerged. In this article one of the major innovation hotspots in the post-Moore era were reviewed: the latest progress of wafer-level three-dimensional integration technology, including aspects such as the design, process, thermal management, reliability, and application innovation of wafer-level three-dimensional integration technology. It also was reviewed and analyzed that the development status and trends of key technologies of wafer-level three-dimensional integration technology in the industrial and research fields in the past three years. The key technological development highlights covered in this article were included: new paths for time Scaling, AI-enabled design tools, TSV and microbump process innovations, industrial implementation of hybrid bonding technology, disruptive breakthroughs in single-chip 3D integration, next-generation co-packaging optical technology, diamond-based heat dissipation, multi-micro-channel cooling, ultra-thin wafer-level integrated heat dissipation, microbump resistance to electromagnetic migration, bonding strength in hybrid bonding interfaces, reduction of thermal mechanical warpage in fan-out wafer-level packaging, wafer-level 3D photonic integration, wafer-level 3D RF electronic integration, wafer-level 3D MEMS integration, and wafer-level 3D AI information processing integration, etc.

Key words: wafer-level three-dimensional integration, design methods and tools, processes, thermal management, reliability