[1] UEDA D, TAKAGI H, KANO G. A new vertical power MOSFET structure with extremely reduced on-resistance[J]. IEEE Transactions on Electron Devices, 1985, 32(1): 2-6.
[2] ZENG J, DOLNY G M, KOCON C B, et al. Power MOS device with buried gate and groove：US6445035B1 [P]. 2002-09-03.
[3] TONG C F, MAWBY P A, COVINGTON J A. ‘Field Balanced’ SG-RSO structure showing tremendous potential for low voltage trench MOSFETs[C]. European Conference on Power Electronics and Applications. IEEE, 2009: 1-5.
[4] GOARIN P, KOOPS G E J, DALEN R V, et al. Split-gate resurf stepped oxide (RSO) MOSFETs for 25 V applications with record low gate-to-drain charge[C]. ISPSD, 2007: 61-64.
[5] ZHANG W T, YE L, FANG D, et al. Model and experiments of small-size vertical devices with field plate[J]. IEEE Transaction on Electron Devices, 2019, 66(3): 1416 -1421.
[6] TONG C F, CORTES I, MAWBY P A, et al. Static and Dynamic Analysis of Split-Gate RESURF stepped oxide (RSO) MOSFETs for 35 V applications[C]. Conference on Electron Devices. IEEE, 2009:250-253.
[7] PARK C, HAVANUR S, SHIBIB A, et al. 60 V rating split gate trench MOSFETs having best-in-class specific resistance and figure-of-merit[C]. ISPSD, 2016:387-390.
[8] WANG Y, LAN H, DOU Z, et al. Method to improve trade-off performance for split-gate power U-shape metal-oxide semiconductor field-effect transistor with compound trench dielectrics[J]. IET Power Electronics, 2014, 7(8):2030-2034.
[9] WANG Y, HU H F, WANG L G, et al. Split gate resurf stepped oxide UMOSFET with P-pillar for improved performance[J]. IET Power Electronics, 2014, 7(4):965-972.
[10] WANG Y, HU H F, DOU Z, et al. Way of operation to improve performance for advanced split-gate resurf stepped oxide UMOSFET[J]. IET Power Electronics, 2014:2964-2968.
[11] WANG Y, HU H F, YU C H, et al. Advanced hexagonal layout design for split-gate reduced surface field stepped oxide U-groove metal–oxide–semiconductor field-effect transistor[J]. IET Power Electronics, 2015, 8(5):678-684.
[12] DENG S L, HOSSAIN Z, TANIGUCHI T. Detailed study on dynamic characteristics of a high-performance SGT-MOSFET with under-the-trench floating p-pillar[J]. IEEE Transaction on Electron Devices, 2017,64(3):735-740.
[13] WANG W, NING R, SHEN Z J. Numerical study of p-n-doped poly-silicon shield gate trench MOSFET with reduced output capacitance[J]. IEEE Electron Device Letters, 2017, 38(8):1055-1058.
[14] HOSSAIN Z, MULLAPUDI R, SURDI H. Diode reverse recovery characteristics of a shielded-gate trench power MOSFET[C]. ISPSD, 2019:383-386.
[15] 叶力. 屏蔽栅VDMOS优值模型与器件结构研究[D].成都：电子科技大学,2019. |
