关键词: UVM, System Verilog语言, PCIe

Abstract: For peripheral component interconnect express (PCIe) bus controller, aiming at the characteristics of complicated data format and various link state, a universal verification methodology (UVM) based System Verilog verification platform is built. Different from traditional directional verification platform, this verification platform generates constrained random test case, verifies PCIe bus controller comprehensively and analyzes result and collects functional coverage automatically. According to the results of verification, this verification platform can efficiently find out bugs in design, fulfill coverage requirement, and improve verification efficiency with excellent configurability and reusability.

Key words: UVM, SystemVerilog, PCIe