关键词: 低压差线性稳压器, 电源完整性, 供电方案, 模数转换器

Abstract: In order to rationally utilize the chassis space and reduce the number of power supply chips, a power supply scheme of 20 analog-to-digital converter (ADC) chips is proposed, which can reduce the possibility of signal interference caused by the same power input of ADC chips in different frequency bands and the number of low dropout linear regulator (LDO), make full use of the power supply capacity of the power chip, and greatly reduce the cost of module development. Compared with the traditional power supply scheme, the number of power chips used in the proposed scheme is reduced by more than half, and the layout area of power supply is reduced by 60%. It can be identified in advance that the 2.5 V voltage output by one LDO chip fails to reach the minimum voltage requirement of the ADC chip input when it reaches the ADC chip through simulation. Combined with static voltage drop formula, three optimization methods are provided, which can meet the minimum voltage requirements of ADC chip input. The second optimization method is adopted in this design. The measured results of the return board show that the voltage difference between the three chips received is 0.3 V, which is consistent with the simulation results.

Key words: lowdropoutlinearregulator, powerintegrity, poweringdesign, analog-to-digitalconverter