中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2025, Vol. 25 ›› Issue (6): 060304 . doi: 10.16257/j.cnki.1681-1070.2025.0060

• 电路与系统 • 上一篇    下一篇

一种支持循环缓冲的中断系统的设计与验证*

沈一帆,谭勋琼   

  1. 长沙理工大学物理与电子科学学院,长沙 410114
  • 收稿日期:2024-11-25 出版日期:2025-06-27 发布日期:2025-01-20
  • 作者简介:沈一帆(2000—),女,河南信阳人,硕士研究生,主要研究方向为高性能DSP处理器设计。

Design and Verification of an Interrupt System Supporting Loop Buffering

SHEN Yifan, TAN Xunqiong   

  1. School of Physics and Electronic Science, Changsha University of Science and Technology, Changsha 410114, China
  • Received:2024-11-25 Online:2025-06-27 Published:2025-01-20

摘要: 针对超长指令字(VLIW)结构高性能数字信号处理器(DSP)设计了高效安全的中断处理系统,支持12级可屏蔽中断、非屏蔽中断(NMI)与软硬件中断嵌套。针对循环缓冲区中断对程序流的破坏,设计了一种专门的中断响应与处理机制,确保在高频中断情况下,循环缓冲区中的数据处理不受中断影响,从而避免数据丢失或程序崩溃。针对VLIW结构的特点,优化了中断处理流程,减少了中断响应延迟。仿真结果表明,本设计的中断响应时间相较传统方法缩短25%,且保证了复杂程序在中断处理时的数据完整性与执行安全性。

关键词: 中断响应, 中断处理, 中断嵌套, 中断返回, 循环缓冲中断

Abstract: An efficient and secure interrupt processing system is designed for high-performance digital signal processor (DSP) based on very long instruction word (VLIW) structure, which supports 12 levels of maskable interrupts, non-maskable interrupts(NMIs), and hardware and software interrupt nesting. To address the disruption of program flow caused by loop buffer interrupts, a special interrupt response and processing mechanism is designed to ensure that in the case of high-frequency interrupts, the data processing in the loop buffer is not affected by interrupts, thus avoiding data loss or program crashes. The interrupt processing flow is optimized based on the characteristics of the VLIW structure, and the interrupt response delay is reduced. Simulation results show that the interrupt response time of this design is 25% shorter than that of the traditional method, and it ensures the data integrity and execution security of complex programs during interrupt processing.

Key words: interrupt response, interrupt processing, interrupt nesting, interrupt return, loop buffer interrupt

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