中国电子学会电子制造与封装技术分会会刊

中国半导体行业协会封测分会会刊

无锡市集成电路学会会刊

导航

电子与封装 ›› 2026, Vol. 26 ›› Issue (3): 030301 . doi: 10.16257/j.cnki.1681-1070.2026.0030

• 电路与系统 • 上一篇    下一篇

一种数字波束合成芯片的FPGA验证系统搭建

杨业,符青,曹靖,王志龙,胡兵,汤涛   

  1. 江苏华创微系统有限公司,南京  210000
  • 收稿日期:2025-08-04 出版日期:2026-04-02 发布日期:2025-12-05
  • 作者简介:杨业(1989—),男,江苏扬州人,硕士,工程师,现从事芯片设计和FPGA原型验证领域工作。

Construction of an FPGA Verification System for Digital Beamforming Chip

YANG Ye, FU Qing, CAO Jing, WANG Zhilong, HU Bing, TANG Tao   

  1. Jiangsu Huachuang Microsystems Co., Ltd., Nanjing 210000, China
  • Received:2025-08-04 Online:2026-04-02 Published:2025-12-05

摘要: 数字波束合成(DBF)芯片是一种复杂的专用集成电路(ASIC)芯片,其流片前的验证工作对提高芯片成功率至关重要。提出了一种基于可编程门阵列(FPGA)的原型验证系统搭建方法,采用思尔芯科技的Quad VU验证板和树莓派开发板,模拟芯片流片后的应用场景。通过合理裁剪芯片设计代码,替换FPGA不可编译的模块,并重新设计时钟架构,实现了数字波束合成芯片在FPGA上的功能验证。实验结果表明,该系统能够有效验证芯片的数据处理流程和多片级联功能,为芯片回片测试奠定了坚实基础。

关键词: 数字波束合成, FPGA验证, 原型, 树莓派, 多片级联

Abstract: The digital beamforming (DBF) chip is a kind of complex application-specific integrated circuit (ASIC) chip, and its verification work before tape-out is crucial to improve the success rate of the chip. A field programmable gate array (FPGA)-based prototyping verification system construction method is proposed. The Quad VU verification board from S2C Technology and a Raspberry Pi development board are employed to simulate the application scenario after tape-out. By reasonably trimming the chip design code, replacing the non-compilable modules for the FPGA, and redesigning the clock architecture, the functional verification of the DBF chip on the FPGA is realized. The experimental results show that the system can effectively verify the data processing flow and multi-chip cascade function of the chip, which lays a solid foundation for chip post-silicon test.

Key words: digital beamforming, FPGA verification, prototyping, Raspberry Pi, multi-chip cascade

中图分类号: