一种应用于高精度流水线ADC的差分参考电压电路*

doi:10.16257/j.cnki.1681-1070.2022.0509

电子与封装 ›› 2022, Vol. 22 ›› Issue (5): 050305 . doi: 10.16257/j.cnki.1681-1070.2022.0509

一种应用于高精度流水线ADC的差分参考电压电路^*

池哲涵;黎飞;刘颖异;唐旭升;苗澎

东南大学微电子学院，江苏无锡　214135

收稿日期:2021-10-25 出版日期:2022-05-26 发布日期:2021-12-14
作者简介:池哲涵（1996—），男，福建三明人，硕士，主要研究方向为数模混合集成电路设计。

A Differential Reference Circuit Applied inHigh Precision Pipelined ADC

CHI Zhehan, LI Fei, LIU Yingyi, TANG Xusheng, MIAO Peng

School of microelectronics, SoutheastUniversity, Wuxi 214135, China

Received:2021-10-25 Online:2022-05-26 Published:2021-12-14

摘要/Abstract

摘要： 设计了一种应用于18位20 MS/s流水线模数转换器（Analog-to-Digital Converter, ADC）的参考电压电路，电路采用源级推挽输出与电压负反馈结构的输出缓冲器，该输出缓冲器具有输出阻抗小、驱动能力高的特点。整体ADC电路采用180 nm 1P6M 5 V CMOS工艺实现，面积为2.50 mm×5.00 mm，其中，参考电压电路面积为0.20 mm×1.05 mm。仿真结果表明，参考电压电路中带隙基准电压在-40~90 ℃内温度系数为5.526×10^-6/℃，应用所设计的参考电压电路，整体ADC在20 MHz采样频率输入信号859.375 kHz下，有效位数（Effective Number of Bits, ENOB）为16.88 bit，信噪比（Signal to Noise Ratio, SNR）为103.41 dB，无杂散动态范围（Spurious Free Dynamic Range, SFDR）为110.69 dB。

关键词: 流水线ADC, 参考电压, 输出缓冲器

Abstract: A reference circuit based on output buffer with source stage push-pull output and voltage negative feedback structure is designed for an 18 bit 20 MS/s pipelined analog-to-digital converter (ADC). The output buffer has the characteristics of small output impedance and high driving ability. The overall ADC circuit is fabricated by 180 nm 1P6M 5 V CMOS process, with an area of 2.50 mm×5.00 mm, of which the reference circuit area is 0.20 mm×1.05 mm. The simulation results show that the temperature coefficient of the bandgap reference voltage is 5.526 ×10^-6/℃ at -40~90 ℃, under the application of the designed reference circuit, the overall ADC has an effective number of bits (ENOB) of 16.88 bit, a signal to noise ratio (SNR) of 103.41 dB and a spurious free dynamic range (SFDR) of 110.69 dB at 20 MHz sampling frequency input signal 859.375 kHz.

Key words: pipelinedADC, referencevoltage, outputbuffer

中图分类号:

TN453

池哲涵;黎飞;刘颖异;唐旭升;苗澎. 一种应用于高精度流水线ADC的差分参考电压电路^*[J]. 电子与封装, 2022, 22(5): 050305 .

CHI Zhehan, LI Fei, LIU Yingyi, TANG Xusheng, MIAO Peng. A Differential Reference Circuit Applied inHigh Precision Pipelined ADC[J]. Electronics & Packaging, 2022, 22(5): 050305 .

参考文献

[1] ALI A M A, DINC H, BHORASKAR P, et al. A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration[J]. IEEE Journal of Solid-State Circuits, 2014, 49(12): 2857-2867.
[2] LI W T, LI F L, YANG C Y et al. An 85 mW 14-bit 150 MS/s pipelined ADC with a merged first and second MDAC[J]. China Communications, 2015, 12(5): 23-30.
[3] ALI A, DILLON C, SNEED R, et al. A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter[J]. IEEE Journal of Solid-State Circuits, 2006, 41(8): 1846-1855.
[4] ALI A. High-performance, low-noise reference generators: US7215182B2[P]. 2007-08-05.
[5] MOK W I, MAK P I, SENG-PAN U, et al. Modeling of noise sources in reference voltage generator for very-high-speed pipelined ADC[C]// The 2004 47th Midwest Symposium on Circuits and Systems, July 25-28, 2004, Hiroshima, Japan. New York: IEEE, 2004: 1-5.
[6] 陈珍海，于宗光，李现坤，等. 用于16-bit 100 MS/s ADC的高精度参考电压产生电路[J]. 西安电子科技大学学报(自然科学版), 2017, 44(3): 127-132, 180.
[7] LI W T, LI F L, YANG C Y, et al. A power-efficient reference buffer with wide swing for switched-capacitor ADC[J]. Microelectronics Journal, 2015, 46(5): 410-414.
[8] SUN J, WU J H. A high speed pipeline ADC with 78-dB SFDR in 0.18 um BiCMOS[C]// 2016 International Symposium on Integrated Circuits (ISIC), Dec. 12-14, 2016, Singapore. New York: IEEE, 2016: 1-4.
[9] SINGER L, HO S, TIMKO M, et al. A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz[J]. 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000: 38-39.
[10] 姜杰，尹文婧，许俊，等. 应用于流水线ADC的参考电压源及其输出缓冲器[J]. 微电子学, 2006, 36(6): 806-809.

中文引用格式：池哲涵，黎飞，刘颖异，等. 一种应用于高精度流水线ADC的差分参考电压电路[J]. 电子与封装，2022, 22(): .
英文引用格式：CHI Zhehan, LI Fei, LIU Yingyi, et al. A differential reference circuit applied in high precision pipelined ADC[J]. Electronics & Packaging, 2022, 22():
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一种应用于高精度流水线ADC的差分参考电压电路^*

A Differential Reference Circuit Applied inHigh Precision Pipelined ADC

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