关键词: 可配置逻辑块, FPGA, 架构建模

Abstract: Configurable logic block (CLB) is the most significant module in FPGA, which mainly consists of look-up tables, multiplexers, flip-flops and other sub-modules that can be configured to implement sequential logic and combinational logic, and its performance directly affects the performance of the whole FPGA. To improve the utilization and performance of CLB, an improved CLB structure is proposed. The modified CLB structure is architecture modeled based on the VPR platform, different types of reference circuits are selected to test the impact of the CLB structure on delay and area performance. The test result shows that the improved structure with 8.86% increase in critical path delay, the number of CLBs saves 24.88% and the area is reduced by 12.95%. And the structure can be correctly described and parsed in VPR, the test results have reference value for the structure design and analysis of FPGA.

Key words: configurable logic block, FPGA, architecture model