中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2019, Vol. 19 ›› Issue (7): 016 -19. doi: 10.16257/j.cnki.1681-1070.2019.0705

• 电路设计 • 上一篇    下一篇

一款10位逐次逼近型模数转换器设计

车来晟,唐鹤,高昂,牛胜普   

  1. 电子科技大学,成都 610054
  • 收稿日期:2019-03-07 出版日期:2019-07-18 发布日期:2019-07-18
  • 作者简介:车来晟(1995—),男,安徽六安人,硕士研究生,研究方向为数模混合集成电路设计。

A 10-bit Successive Approximation Analog-to-Digital Converter

CHE Laisheng,TANGHe,GAO Ang,NIU Shengpu   

  1. University of Electronic Scienceand Technology of China,Chengdu 610054,China
  • Received:2019-03-07 Online:2019-07-18 Published:2019-07-18

摘要: 基于0.18μm CMOS工艺设计一款10位逐次逼近型模数转换器(SARADC),采用了阻容混合型的数模转换器(DAC)以实现面积与性能上的折衷,高位采用温度码设计以提高DAC的线性度。采用了失调电压较小的静态比较器结构,通过在DAC和比较器之间加入了高增益的前置放大器来消除比较器失调电压对ADC性能所带来的影响。仿真结果表明:在电源电压为2.8 V、采样速率为116 kS/s、输入信号频率约为57 kHz、满摆幅为0.8 V的情况下,ADC有效位数(ENOB)达9.99位,信噪失真比(SNDR)为61.9dB,无杂散动态范围(SFDR)为75.57dB,总功耗约为1mW,面积为0.069 mm2

关键词: A/D转换器, 逐次逼近型ADC, 阻容混合型DAC, 温度码

Abstract: A 10 bit successive approximation analog-to-digital converter(SAR ADC)based on a 0.18μm CMOSprocessispresented.Theproposed SARADCemploysa RC-capabledigital-to-analog converter(DAC)to achievethetrade-off between areaand performance,and the high bitsof the DACemploy temperaturecodes to improvethelinearity of the DAC.A static comparator structurewith small offset voltageisused in the ADC,and ahigh-gain pre-amplifier isadded between the DACand thecomparator to eliminate the effectscaused by comparator offset voltage on the ADC performance.The simulation results show that the effective number of bits(ENOB)of the ADCis9.99 bitsand the signal-to-noise ratio(SNDR)is61.9 dB when the power supply voltageis2.8 V,thesampling rateis116 kS/s,theinputsignal frequency isabout57 kHz,and theswing is0.8 V.Spurious-freedynamic range(SFDR)is75.57 dB,thetotal power consumption isapproximately 1 mW,and the areais0.069mm2.

Key words: A/Dconverter, SARADC, RC-capable DAC, temperaturecode

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