[1] ZHAO Y, HAO C, YOSHIMURA T. Thermal and
wirelength optimization with TSV assignment for 3-D IC[J]. IEEE Trans on
Electron Devices, 2019, 66(1): 625-632.
[2] REN Z, ALQAHTANI A, BAGHERZADEH N, et al.
Thermal TSV optimization and hierarchical floor planning for 3-D integrated
circuits[J]. IEEE Trans. on Components, Packaging and Manufacturing Technology,
2020, 10(4): 599-610.
[3] XIE J, SWAMINATHAN M. Electrical-thermal
co-simulation of 3D integrated systems with micro-fluidic cooling and joule
heating effects[J]. IEEE Trans on Components, Packaging and Manufacturing
Technology, 2011, 1(2):234-246.
[4] LIU Z, SWARUP S, TAN S X, et al. Compact
lateral thermal resistance model of TSVs for fast finite-difference based
thermal analysis of 3-D stacked ICs[J]. IEEE Trans on Computer-Aided Design of
Integrated Circuits and Systems, 2014, 33(10):1490-1502.
[5] CHAI J, DONG G, YANG Y. An effective approach
for thermal performance analysis of 3-D integrated circuits with
through-silicon vias[J]. IEEE Trans on Components, Packaging and Manufacturing
Technology, 2019, 9(5):877-887.
[6] MUZYCHKA Y S, BAGNALL K R, WANG E N.
Thermal spreading resistance and heat source temperature in compound
orthotropic systems with interfacial resistance[J]. IEEE Trans on Components,
Packaging and Manufacturing Technology, 2013, 3(11):1826-1841.
[7] CHOOBINEH L, JAIN A. Analytical solution
for steady-state and transient temperature fields in vertically stacked 3-D
integrated circuits[J]. IEEE Trans on Components, Packaging and Manufacturing
Technology, 2012, 2(12):2031-2039.
[8] CHOOBINEH L, JAIN A. An explicit analytical
model for rapid computation of temperature field in a three-dimensional
integrated circuit(3D IC)[J]. International Journal of Thermal Sciences, 2015,
87(1):103-109.
[9] WANG K, PAN Z. An analytical model for
steady-state and transient temperature fields in 3-D integrated circuits[J].
IEEE Trans on Components, Packaging and Manufacturing Technology, 2016,
6(7):1026-1039.
|
