中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2021, Vol. 21 ›› Issue (2): 020401 . doi: 10.16257/j.cnki.1681-1070.2021.0209

• 微电子制造与可靠性 • 上一篇    

基于GaAs背孔工艺监控研究

黄光伟,马跃辉,陈智广,李立中,林伟铭   

  1. 福联集成电路有限公司,福建 莆田 351111
  • 收稿日期:2020-08-01 出版日期:2021-02-24 发布日期:2020-09-22
  • 作者简介:黄光伟(1995—),男,福建莆田人,本科,现从事GaAs半导体工艺开发工作。

Research on BackHole Process Monitoring Based on GaAs

HUANG Guangwei, MA Yuehui, CHEN Zhiguang, LEE Luke, LIN Vanhalen   

  1. UniCompound Integrated Circuit Co., Ltd., Putian 351100, China
  • Received:2020-08-01 Online:2021-02-24 Published:2020-09-22

摘要: 在GaAs背孔工艺制作中,通孔良率影响着后续溅镀、电镀金属层与正面金属互联,在该道关键制程中缺乏有效的监控方法。在背孔工艺中,采用FIB、SEM的方式对ICP蚀刻后的晶圆进行裂片分析,这无疑大大增加了研发成本,裂片分析也仅仅是当前晶圆的通孔良率,且分析孔洞数量有限,本身存在局限。提出在晶圆正面依次沉积Si3N4/PI/Si3N4 =600 nm/1.6 μm/800 nm,采用ICP蚀刻,蚀刻气体为Cl2/BCl3,在光学显微镜(OM)20倍率下便可观察到晶圆正面第一特征蚀刻通孔印记和印记尺寸较原始尺寸单边大10 μm的第二通孔特征,该监控方式节省研发成本且统计良率直观,可及时反馈通孔良率,监控产品的可靠性、可再现性。

关键词: 砷化镓, 背孔, 良率, 监控, ICP蚀刻

Abstract: In the fabrication of GaAs back hole process, the through-hole yield affects the subsequent splashing, plating metal layer and front metal interconnection, and there is no effective monitoring method in the key process. In the back hole process, FIB and SEM are used to analyze the chips etched by ICP, which undoubtedly greatly increases the cost of research and development. The chip analysis is only the through-hole yield of the current wafer, and the number of analysis holes is limited, which has its own limitations. In this paper, Si3N4 / PI / Si3N4 =600 nm/1.6 μm/800 nm is deposited on the front of the wafer by ICP, the etching gas is Cl2 / BCl3. Under the OM×20 ratio, the first feature of the wafer front etching through-hole mark and the second through-hole feature whose mark side size is 10 μm larger than the original size can be observed. This monitoring method saves cost and has intuitive statistical yield, timely feedbacks the through-hole yield and monitors the reliability and reproducibility of the product.

Key words: GaAs, Dorsalforamen, Yield, Monitor, ICPetching

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