众核任务映射算法研究现状与发展趋势*

doi:10.16257/j.cnki.1681-1070.2022.0207

摘要/Abstract

摘要： 在众核系统中，并行任务在执行前需要被映射到处理器，这一过程被称为任务映射，任务映射算法对芯片性能影响巨大，所以近年来众核任务映射算法成为研究热点。针对不同的系统架构（如二维和三维众核系统）和优化目标（如通信开销、功耗、温度等）对现有任务映射算法进行综述，并展望了任务映射算法的未来发展趋势。

关键词: 任务映射, 众核, 资源管理

Abstract: In many-core systems, parallel tasks need to be mapped to processors before execution, which is referred as task mapping. Task mapping algorithms have a great impact on chip performance, and thus have attracted enthusiasm in the research community. Existing task mapping algorithms for different system architectures (such as 2D and 3D many-core systems) and optimization objectives (such as communication overhead, power consumption, temperature, etc.) are reviewed, and future research trends of task mapping algorithms are provided.

Key words: taskmapping, many-core, resourcemanagement

中图分类号:

TN402

吴倩, 王小航. 众核任务映射算法研究现状与发展趋势^*[J]. 电子与封装, 2022, 22(2): 020305 .

WU Qian, WANG Xiaohang. Current and Emerging Trendsof Task Mapping in Many-Core Systems[J]. Electronics & Packaging, 2022, 22(2): 020305 .

参考文献

[1] FATTAH M, RAMíREZ M, DANESHTALAB M, et al. CoNA: Dynamic application mapping for congestion reduction in many-core systems[C]// International Conference on Computer Design (ICCD), 2012: 364-370.
[2] FATTAH M, DANESHTALAB M, LILJEBERG P, et al. Smart hill climbing for agile dynamic mapping in many-core systems[C]// ACM/EDAC/IEEE Design Automation Conference, 2013: 10-15.
[3] ANAGNOSTOPOULOS I, TSOUTSOURAS V, BARTZAS A, et al. Distributed run-time resource management for malleable applications on many-core platforms[C]// Design Automation Conference (DAC), 2013: 1-6.
[4] NG J, WANG X, SINGH A, et al. Defragmentation for efficient runtime resource management in NoC-based many-core systems[C]// IEEE Transactions on Very Large Scale Integration Systems, 2016: 3359-3372.
[5] WANG X, FEI T, ZHANG B, et al. On runtime adaptive tile defragmentation for resource management in many-core systems[C]// Microprocessors and Microsystems - Embedded Hardware Design, 2016: 161-174.
[6] PATHANIA A, VENKATARAMANI V, SHAFIQUE M, et al. Defragmentation of tasks in many-core architecture[C]// ACM Transactions on Architecture and Code Optimization, 2017: 1-21.
[7] HUANG L, YUAN F, XU Q. Lifetime reliability-aware task allocation and scheduling for MPSoC platforms[C]// Design Automation, and Test in Europe, 2009: 51-56.
[8] WANG L, LV P, LIU L, et al. A lifetime reliability-constrained runtime mapping for throughput optimization in many-core systems[C]// IEEE Trans CAD Integrated Circuits Syst, 2019: 1771-1784.
[9] WANG L, JIANG S, CHEN S, et al. Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system[C]// Integration, 2019: 6782-6794.
[10] KAPADIA N, PASRICHA S. A runtime framework for robust application scheduling with adaptive parallelism in the dark-silicon era[J]. IEEE Transactions on Very Large Scale Integration Systems, 2016, 25(2): 534-546.
[11] KRIEBEL F, REHMAN S, SUN D. Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era[C]// IEEE Design Automation Conference (DAC), 2014: 1-6.
[12] KAPADIA N A, PASRICHA S. VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era[C]// Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015: 1060-1065.
[13] SHAFIQUE M, GNAD D, GARG S, et al. Variability-aware dark silicon management in on-chip many-core systems[C]// Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015: 387-392.
[14] HOVEIDA M, AGHAALIAKBARI F, BASHIZADE R, et al. Efficient mapping of applications for future chip multiprocessors in dark silicon era[J]. ACM Transactions on Design Automation of Electronic Systems, 2017, 22(4): 1-26.
[15] BHARATHWAJ R, SIDDHARTH G. Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era[C]// International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2014: 1-9.
[16] MUHAMMAD U, MUHAMMAD S, J?RG H. Power-efficient accelerator allocation in adaptive dark silicon many-core systems[C]// Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015: 916-919.
[17] ANIL K. Dark silicon aware runtime mapping for many-core systems: A patterning approach[C]// Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD’15). IEEE, 2015: 573-580.
[18] ANIL K, MOHAMMAD H, AMIR M, et al. thermal aware performance boosting through dark silicon patterning[C]// IEEE Transactions on Computers, 2018: 1062-1077.
[19] ANUP D, AKASH K, BHARADWAJ V. Reliability and energy-aware mapping and scheduling of multimedia applications on multiprocessor systems[C]// IEEE Transactions on Parallel and Distributed Systems, 2016: 869-884.
[20] THIDAPAT C, HU X, ROBERT P. Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs[C]// IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011: 1884-1897.
[21] JUNLONG Z, JIANMING Y, JING C. Peak temperature minimization via task allocation and splitting for heterogeneous MPSoC real-time systems[J]. Journal of Signal Processing Systems., 2016: 111-121.
[22] ARYABARTTA S. Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessor[C]// Design, Automation, and Test in Europe, 2016: 1096-1101.
[23] MAJED V, GOKHAN M. Thermal-aware run-time thread migration for interconnects[C]// International Symposium on Low Power Electronics and Design, 2016: 230-235.
[24] BAGHER S, MOHAMMADREZA B, HAMID N. Physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors[C]// Asia and South Pacific Design Automation Conference. 2014: 292-297.
[25] YOUNG G, MINYONG K, JAE M. M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processors[C]// Design, Automation, and Test in Europe (DATE), 2015: 1533-1538.
[26] HANWOONG J, CHANHEE L, SHIN-HAENG K, et al. Dynamic behavior specification and dynamic mapping for real-time embedded systems: Hopes approach[C]// ACM Transactions on Embedded Computing Systems, 2014: 1-26.
[27] MENGQUAN L, WEICHEN L, LEI Y, et al. Chip temperature optimization for dark silicon many-core systems[C]// IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018: 941-953.
[28] MD F, DAN Z, MAGDY B, Dark silicon-power-thermal aware runtime mapping and configuration in heterogeneous many-core NoC[C]// IEEE International Symposium on Circuits and Systems (ISCAS), 2017: 1-4.
[29] FATEMEH A, MOHADDESEH H, MOHAMMAD A, et al. Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era[C]// International Conference on Computer Design (ICCD), 2016: 336-343.
[30] WEICHEN L, LEI Y, WEIWEN J, et al. Thermal-aware task mapping on dynamically reconfigurable Network on Chip based multiprocessor system on chip[C]// IEEE Transactions on Computers, 2018: 1818-1834.
[31] MD F, DAN Z, MAGDY A. Power-thermal aware balanced task-resource co-allocation in heterogeneous many CPU-GPU cores NoC in dark silicon era[C]// IEEE International System on Chip Conference (SOCC), 2018: 260-265.
[32] DING H, GU H, YANG Y, et al. 3D networks-on-chip mapping targeting minimum signal TSVs[J]// IEICE Electron Express, 2013, 10(18): 20130518.
[33] MANNA K, SWAMI S, CHATTOPADHYAY S, et al. Integrated through-silicon via placement and application mapping for 3D mesh-based NoC design[J]. ACM Transactions on Embedded Computing Systems, 2016, 16(1): 1-25.
[34] JHA V, DEOL S, JHA M, et al. Energy and latency aware application mapping algorithm & optimization for homogeneous 3D Network on Chip[J]. Computing Research Repository, 2014, arXiv: 1404.2512.
[35] AGYEMAN M O, AHMADINIA A, Bagherzadeh N. Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip[J]. Journal of Systems Architecture, 2018, 89: 103-117.
[36] ELMILIGI H, GEBALI F, EL-KHARASHI M W. Power-aware mapping for 3D-NoC designs using genetic algorithms[J]. FNC/MobiSPC, 2014, 34: 538-543.
[37] 王源. 非规则拓扑的三维片上网络低功耗映射优化[D]. 西安: 西安电子科技大学, 2018: 5-12.
[38] RAPARTI V Y, KAPADIA N A, PASRICHA S. ARTEMIS: An aging-aware runtime application mapping framework for 3D NoC-based chip multiprocessors[J]. IEEE Transactions on Multi-Scale Computing Systems, 2017, 3(2): 72-85.
[39] FENG G, GE F, YU S, et al. A thermal-aware mapping algorithm for 3D mesh network-on-chip architecture[C]// IEEE International Conference on ASIC, Shenzhen, China: IEEE, 2013: 1-4.
[40] WANG X, JIANG Y, YANG M, et al. HRC: A 3D NoC architecture with genuine support for runtime thermal-aware task management[J]. IEEE Transactions on Computers, 2017, 66(10): 1676-1688.
[41] DEMIRIZ A, AHANGARI H, OZTURK O. Temperature-aware core mapping for heterogeneous 3D NoC design through constraint programming[C]// Euromicro International Conference on Parallel, Distributed and Network-Based Processing, Sweden: IEEE, 2020: 312-318.
[42] MOSAYYEBZADEH A, AMIRASKI M M, HESSABI S. Thermal and power aware task mapping on 3D Network on chip[J]. Computers and Electrical Engineering, 2016, 51: 157-167.
[43] LI B, WANG X, SINGH A K, et al. On runtime communication and thermal-aware application mapping and defragmentation in 3D NoC systems[J]. IEEE Transactions on Parallel and Distributed Systems, 2019, 30(12): 2775-2789.
[44] DING H, GU H, YANG Y, et al. 3D networks-on-chip mapping targeting minimum signal TSVs[J]. IEICE Electron Express, 10(18): 20130518.
[45] HAGHBAYANM. H, MIELE A, RAHMANI A, et al. A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era[C]// Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016: 854-857.
[46] HAGHBAYANM H, RAHMANIA M. Can dark silicon be exploited to prolong system lifetime?[C]// IEEE Design & Test, 2018: 51-59.
[47] HAGHBAYANM H, MIELE A, RAHMANI A M, et al. Performance/reliability-aware resource management for many-cores in dark silicon era[C]// IEEE Transactions on Computers, 2009:1599-1612.
[48] DENNIS G, MUHAMMAD S, FLORIAN K, et al. Hayat: Harnessing dark silicon and variability for aging deceleration and balancing[C]// ACM/EDAC/IEEE Design Automation Conference (DAC), 2015: 1-6.
[49] RATHORE V, CHATURVEDI V, SINGH A. K, et al. HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems[C]// Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018: 991-996.

中文引用格式：吴倩，王小航. 众核任务映射算法研究现状与发展趋势[J]. 电子与封装，2022，22（5）：050302.
英文引用格式:WU Qian, WANG Xiaohang. Current and emerging trends of task mapping in many-core systems[J]. Electronics & Packaging, 2022, 22(5): 050302.
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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

众核任务映射算法研究现状与发展趋势^*

Current and Emerging Trendsof Task Mapping in Many-Core Systems

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