基于分解的多路选择器工艺映射方法设计

doi:10.16257/j.cnki.1681-1070.2022.0807

电子与封装 ›› 2022, Vol. 22 ›› Issue (8): 080302 . doi: 10.16257/j.cnki.1681-1070.2022.0807

基于分解的多路选择器工艺映射方法设计

谢尚銮;惠锋;刘佩;王晨阳;张立

无锡中微亿芯有限公司，江苏无锡　214072

收稿日期:2022-01-13 出版日期:2022-08-26 发布日期:2022-05-26
作者简介:谢尚銮（1996—），男，浙江温州人，硕士，助理工程师，现从事EDA开发工作。

Design of Technology Mapping Method Based on Decomposition for Multiplexers

XIE Shangluan, HUI Feng, LIU Pei, WANG Chenyang, ZHANG Li

East Technology, Inc., Wuxi 214072, China

Received:2022-01-13 Online:2022-08-26 Published:2022-05-26

摘要/Abstract

摘要： 针对Virtex-7系列FPGA架构，提出了一种基于分解的多路选择器工艺映射方法。选取多个细粒度规则多路选择器作为基准单元，将对应的优质工艺网表保存为模板，将N选1多路选择器递归分解为若干层紧密连接的基准单元并基于模板实现其优化映射。对比所提方法与综合工具Vivado及ABC的多路选择器工艺映射效果，实验数据表明该方法与Vivado相比可平均减少1.01%的查找表（LUT）开销与5.61%的时延，与ABC相比可平均减少20.82%的LUT开销与29.51%的时延，而且该方法时间复杂度低，平均运行速度比ABC快4.28倍。

关键词: FPGA, 多路选择器, 工艺映射, 分解

Abstract: Targeting at the hardware structure of Virtex-7 series FPGA, a decomposition-based technology mapping method for multiplexers is proposed. Specified fine-grained full-multiplexers are chosen as reference cells, and their high-quality technology netlists are saved as templates. N-to-1 multiplexers are recursively decomposed into several levels of cohesive reference cells. The templates are employed to accomplish the technology mapping of N-to-1 multiplexers. Multiplexers mapping results of the proposed method and synthesis tools of Vivado and ABC are compared, and experimental results show that the proposed method can reduce look-up table (LUT) utilization by 1.01% and decrease circuit delay by 5.61% on average compared with Vivado, and outperform ABC in the same comparison parameters by 20.82% and 29.51% respectively. Meanwhile, owing to the low time complexity of this method, its running speed is 4.28 times faster than ABC on average.

Key words: FPGA, multiplexer, technology mapping, decomposition

中图分类号:

TN402

谢尚銮;惠锋;刘佩;王晨阳;张立. 基于分解的多路选择器工艺映射方法设计[J]. 电子与封装, 2022, 22(8): 080302 .

XIE Shangluan, HUI Feng, LIU Pei, WANG Chenyang, ZHANG Li. Design of Technology Mapping Method Based on Decomposition for Multiplexers[J]. Electronics & Packaging, 2022, 22(8): 080302 .

参考文献

[1] Kubica M, Kania D. Area-oriented technology mapping for LUT-based logic blocks[J]. International Journal of Applied Mathematics and Computer Science, 2017, 27(1): 207-222.
[2] Schmitt B, Mishchenko A, Brayton R. SAT-based area recovery in structural technology mapping[C]// 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2018: 586-591.
[3] 余超凡. FPGA工艺映射算法的优化研究[D]. 上海: 复旦大学, 2014.
[4] JAMIESON P, KENT K B, GHARIBIAN F, et al. Odin II - an open-source Verilog HDL synthesis tool for CAD research[C]// IEEE International Symposium on Field-programmable Custom Computing Machines. IEEE, 2010: 149-156.
[5] 路宝珠, 杨海钢, 郝亚男, 等. 基于区域重组的异构FPGA工艺映射算法[J]. 计算机辅助设计与图形学学报, 2012, 24(8): 1027-1037.
[6] 路宝珠, 杨海钢, 郝亚男, 等. 面向算术单元的FPGA工艺映射算法[J]. 微电子学与计算机, 2012, 29(12): 1-6.
[7] 徐宇, 林郁, 杨海钢. FPGA双端口存储器映射优化算法[J]. 电子与信息学报, 2020, 42(10): 2549-2556.
[8] Purnaprajna M, Ienne P. A case for heterogeneous technology-mapping: Soft versus hard multiplexers[C]// 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines. IEEE, 2013: 53-56.
[9] Kohutka L, Pistek P. Faster synthesis of combinational logic based on multiplexer trees and binary decision diagrams[C]// IEEE International Conference on Emerging eLearning Technologies & Applications. IEEE, 2014: 239-244.
[10] MOHAMED A B M, NOOR M S. High speed multiplexer design using tree based decomposition algorithm[J]. Microelectronics Journal, 2016, 51: 99-111.
[11] 兰风宇. Xilinx Virtex-7 FPGA软错误减缓技术研究[D]. 哈尔滨: 哈尔滨工业大学, 2016.
[12] Thakur S, Wong D F, Krishnamoorthy S. Delay minimal decomposition of multiplexers in technology mapping[C]// 33rd Design Automation Conference Proceedings. IEEE, 1996: 254-257.
[13] Metzgen P, Nancekievill D. Multiplexer restructuring for FPGA implementation cost reduction[C]// Proceedings of the 42nd Annual Design Automation Conference, 2005: 421-426.
[14] Mitra S, Avya L J, McCluskey E J. Efficient multiplexer synthesis techniques[J]. IEEE Design & Test of Computers, 2000, 17(4): 90-97.
[15] Brayton R, Mishchenko A. ABC: An academic industrial-strength verification tool[C]// International Conference on Computer Aided Verification. Springer, Berlin, Heidelberg, 2010: 24-40.
[16] Xilinx Inc. UG893-Vivado design suite user guide: Using the Vivado IDE[EB/OL]. (2021-11-6)[2022-2-17]. https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2021_2/ug893-vivado-ide.pdf.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

基于分解的多路选择器工艺映射方法设计

Design of Technology Mapping Method Based on Decomposition for Multiplexers

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