一种JPEG-XS编码器的硬件架构优化设计

doi:10.16257/j.cnki.1681-1070.2025.0023

电子与封装 ›› 2025, Vol. 25 ›› Issue (2): 020304 . doi: 10.16257/j.cnki.1681-1070.2025.0023

一种JPEG-XS编码器的硬件架构优化设计

李雅欣,吴林煌,刘伟,郑畅

福州大学物理与信息工程学院，福州 350108

收稿日期:2024-09-20 出版日期:2025-02-27 发布日期:2025-02-27
作者简介:李雅欣（2000—），女，福建三明人，硕士研究生，主要研究方向为视频编码、FPGA设计。

Optimized Design of Hardware Architecture for JPEG-XS Encoder

LI Yaxin, WU Linhuang, LIU Wei, ZHENG Chang

College of Physics and Information Engineering, Fuzhou University, Fuzhou 350108, China

Received:2024-09-20 Online:2025-02-27 Published:2025-02-27

摘要/Abstract

摘要： 为将JPEG-XS这一主流的浅压缩算法与现场可编程门阵列（FPGA）相结合，设计了一种适用于高分辨率、高帧率应用场景的视频编码器，提出了一种完整的JPEG-XS编码器硬件方案。对整个编码器进行流水线编码设计，实现模块间时间上的复用，对于模块内部，提出了4行并行计算的5/3小波变换架构，对于耗时最长的熵编码模块提出了并行编码各子包的硬件方案。实验结果表明，在Xilinx UltraScale+ ZCU102的FPGA平台，该硬件架构仅占用38.9×10³个查找表资源和23.8×10³个寄存器资源，最大主频可达182.24 MHz，可支持4K@60帧/s的实时编码。

关键词: JPEG-XS, 硬件架构, 现场可编程门阵列, 并行度

Abstract: A video encoder suitable for high-resolution and high frame rate application scenarios is designed to combine the mainstream shallow compression algorithm JPEG-XS with field programmable gate array (FPGA), and a complete hardware solution for the JPEG-XS encoder is proposed. A pipeline encoding for the entire encoder is designed to achieve time reuse between modules. For the internal modules, a 5/3 wavelet transform architecture with 4-line parallel computing is proposed. For the entropy encoding module, which takes the longest time, a hardware solution for parallel encoding of each sub packet is proposed. The experimental results show that on the FPGA platform of Xilinx UltraScale+ZCU102, this hardware architecture only occupies 38.9×10³lookup table resources and 23.8×10³ register resources, with a maximum clock frequency of 182.24 MHz, which can support real-time encoding of 4K@ 60 frame/s.

Key words: JPEG-XS, hardware, FPGA, parallelism

中图分类号:

李雅欣,吴林煌,刘伟,郑畅. 一种JPEG-XS编码器的硬件架构优化设计[J]. 电子与封装, 2025, 25(2): 020304 .

LI Yaxin, WU Linhuang, LIU Wei, ZHENG Chang. Optimized Design of Hardware Architecture for JPEG-XS Encoder[J]. Electronics & Packaging, 2025, 25(2): 020304 .

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一种JPEG-XS编码器的硬件架构优化设计

Optimized Design of Hardware Architecture for JPEG-XS Encoder

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