关键词: JPEG-XS, 解码器, FPGA, 视觉无损, 硬件架构

Abstract: JPEG-XS video codec standard is characterized by high quality, low complexity and low latency. Aiming at the JPEG-XS image codec compression standard, its decoding algorithm is briefly introduced, and a high-performance JPEG-XS decoder architecture oriented to hardware implementation is proposed. The designed decoder hardware architecture adopts pipelined processing, which is able to reduce the path delay caused by combinational logic while maintaining a high data throughput, increase the operating frequency, and decode four reconstructed pixel values per clock cycle. The experimental results show that the designed high-performance JPEG-XS decoder hardware architecture occupies only 15k look-up tables and 10k register resources on the experimental platform of Xilinx Zynq FPGA, with a maximum main frequency of 254 MHz, and can support up to 4K and 100 frame/s real-time video decoding.

Key words: JPEG-XS, decoder, FPGA, visually lossless, hardware architecture