关键词: SAR ADC, 高速, M开关切换策略, 动态比较器

Abstract: A high-speed successive approximation register (SAR) analog-to-digital converter (ADC) based on a VCM switching strategy is proposed. An improved dual-tailed current source dynamic comparator is employed, featuring a dual-current-source cross-latch structure that accelerates comparison speed while eliminating static power consumption, thereby enhancing the overall speed of the SAR ADC. Simultaneously, the VCM switching strategy resolves excessive power consumption during capacitor array switching and common-mode drift at the comparator input. Capacitor splitting technology overcomes the difficulty of designing VCM levels independently, simplifying the timing logic design for switching circuits. Based on SMIC's 130 nm process, simulations were conducted for a 1024-point fast Fourier transform (FFT) at a 1.2 V supply voltage and 50 MS/s sampling rate. Results show that at low input frequencies (244.14 kHz), the ADC achieves an effective number of bits (ENOB) of 9.73 bits, a signal-to-noise distortion ratio (SNDR) of 60.34 dB, a spur-free dynamic range (SFDR) of 73.72 dBc, and total power consumption of 0.95 mW.

Key words: SAR ADC, high speed,  VCM-based switching strategy,  dynamic comparator