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中国电子学会电子制造与封装技术分会会刊

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一种校验码独立存储的EDAC设计

徐文龙,李洪昌,许峥,姚进,周昕杰   

  1. 中国电子科技集团公司第五十八研究所,江苏 无锡  214072
  • 收稿日期:2025-11-10 修回日期:2025-12-02 出版日期:2025-12-05 发布日期:2025-12-05
  • 通讯作者: 徐文龙

EDAC Design with Independent Check Code Storage

XU Wenlong, LI Hongchang, XU Zheng, YAO Jin, ZHOU Xinjie   

  1. China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214072, China
  • Received:2025-11-10 Revised:2025-12-02 Online:2025-12-05 Published:2025-12-05

摘要: 通过引入校验码的检错纠错机制可有效增强存储器的抗单粒子翻转能力。然而,传统架构下校验码与数据码共置于同一存储单元,存在高能粒子同时诱发二者翻转的潜在风险。针对该问题,提出一种基于SRAM的校验码独立存储架构,采用专用存储器单元管理校验码。仿真结果表明,该设计能够有效纠正1比特错误和检测2比特错误;性能方面,面积与功耗无显著增加,故障注入仿真的单粒子翻转率由3.96%降至0.00%。

关键词: 汉明码, 检错纠错, 校验码, 独立存储

Abstract: The error detection and correction mechanism by introducing check codes can effectively enhance the memory's ability to resist single particle flipping. However, in traditional architectures, the checksum and data code are stored in the same unit, which poses a potential risk of high-energy particles simultaneously triggering the flipping of both. A verification code independent storage architecture based on SRAM is proposed to address this issue, using dedicated memory units to manage verification codes. The simulation results show that the design can effectively correct 1-bit errors and detect 2-bit errors; In terms of performance, there is no significant increase in area and power consumption, and the single particle flipping rate of fault injection simulation decreases from 3.96% to 0.00%.

Key words: hamming code, error detection and correction, check code, independent storage