中国电子学会电子制造与封装技术分会会刊

中国半导体行业协会封测分会会刊

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电子与封装

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论韬(τ)定律底层核心技术及创新玻璃基封装

刘复汉1,彭博方2   

  1. 1. 北京清大博联科技中心,北京  100081,2. 上海澈芯科技有限公司,上海  200090
  • 收稿日期:2026-06-10 修回日期:2026-07-01 出版日期:2026-07-06 发布日期:2026-07-06
  • 通讯作者: 刘复汉

On the Underlying Core Technology of τ (tau) - Law and Innovative Glass-Based Packaging

LIU Fuhan1, PENG Bofang2   

  1. 1. Beijing Tsingda Doctours Union Technology CenterBeijing 100081, China; 2. Shanghai Purechip Technology Co., Ltd., Shanghai 200091, China
  • Received:2026-06-10 Revised:2026-07-01 Online:2026-07-06 Published:2026-07-06

摘要: 人类大脑思维存在一个普适的“优先选择”原则:效率最高,价值最大,然而不同方法导致的结果不尽相同,睿智的思维才能引领出一片新天地。华为最新发表了关于韬(τ)定律的主题演讲,阐述了创新的逻辑思维变换和逻辑折叠(Logic Folding)技术,在没有使用昂贵的极紫外(EUV)光刻机及相应配套设备和材料的条件下,经过6年的实践,完成了麒麟芯片-2026和麒麟芯片-2027的流片,华为在演讲中披露在固定工艺节点下,实现了半导体芯片晶体管密度提升55%,能效比提升41%,和主频提升13%,以及在采用智能冗余技术的情况下良率达到近乎100%。其晶体管密度已接近台积电3 nm制程(N3)的水平,预计2031年将进一步提升至等效1.4 nm(N1.4)制程的新高度。这是半导体领域一项新的创新,它将深刻改变从设计软件,生产工艺到设备以及随后的先进封装在内的整个电子系统生态体系, ASML的极紫外EUV光刻机垄断地位也将受到挑战。

关键词: 韬(τ)定律, 半导体, 芯片, EUV, 玻璃基板, 先进封装

Abstract: The human brain's thinking process follows a universal "priority selection" principle:  maximum efficiency and greatest value. However, different approaches yield different outcomes, and only wise thinking can lead to new horizons. Huawei has recently delivered a keynote speech on the τ (tau) Law, elucidating the innovative logical thinking transformation and Logic Folding technology. After six years of practice, without using expensive extreme ultraviolet (EUV) lithography machines or their associated supporting equipment and materials, Huawei has completed the tape-out of the Kirin chip-2026 and Kirin chip-2027. During the speech, Huawei disclosed that at a fixed process node, it has achieved a 55% increase in transistor density, a 41% improvement in energy efficiency ratio, and a 13% boost in clock frequency, while attaining a yield rate of nearly 100% through the adoption of intelligent redundancy technology. The transistor density is now approaching that of TSMC's 3nm process (N3),  and is expected to further reach the equivalent of a 1.4nm (N1.4) process node by 2031. This represents a novel innovation in the semiconductor field, which will profoundly reshape the entire electronic system ecosystem—from design software and manufacturing processes to equipment and subsequent advanced packaging. ASML's monopoly position on EUV lithography will also face significant challenges.

Key words: τ (tau)-law, semiconductor, chip, EUV, glass substrate, advanced packaging