中国电子学会电子制造与封装技术分会会刊

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电子与封装

• 电路与系统 •    下一篇

基于门级网表的抗辐照三模冗余加固设计

姜赛男,谢雨蒙,陆芒芒   

  1. 中国电子科技集团公司第五十八研究所,江苏 无锡  214035
  • 收稿日期:2026-06-16 修回日期:2026-07-17 出版日期:2026-07-23 发布日期:2026-07-23
  • 通讯作者: 姜赛男

Radiation-hardening Triple Modular Redundancy Design for Gate Level Netlist

JIANG Sainan, XIE Yumeng, LU Mangmang   

  1. China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214035, China
  • Received:2026-06-16 Revised:2026-07-17 Online:2026-07-23 Published:2026-07-23

摘要: 集成电路在面向宇航应用时,工作在辐射环境中,容易受到单粒子效应的影响,引起系统的可靠性问题。在集成电路设计阶段,通常可采用三模冗余技术,进行抗辐照设计加固。但现有的三模冗余加固设计,需要针对电路在前端进行定制化设计,与通用设计流程兼容性差,设计效率低。本文提出了一种利用工具对前端门级网表进行处理,实现三模冗余设计的抗辐照加固方法。测试结果表明,通过增加241%的面积代价,经过设计加固的电路单粒子翻转错误率小于1×10-10 error/(bit·day),单粒子闩锁的阈值大于75 MeV·cm2/mg,满足抗辐照接口电路应用需求。

关键词: 抗辐照加固, 三模冗余, 接口电路

Abstract: Integrated circuits operating in radiation environments for aerospace applications are susceptible to single-event effects, which can compromise system reliability. In the integrated circuit design phase, triple modular redundancy (TMR) is commonly adopted for radiation-hardened design. However, existing TMR-based radiation-hardened designs require customized front-end circuit design, which suffers from poor compatibility with general design flows and low design efficiency. This paper presents a radiation hardening method that implements triple modular redundancy by processing front-end gate-level netlists with an automated tool. Test results show that with an area overhead of 241%, the hardened circuit achieves a single-event upset (SEU) error rate lower than 1×10-10 error/(bit·day), and its single-event latch up (SEL) threshold exceeds 75 MeV·cm²/mg. The proposed method fully meets the application requirements of radiation-hardened interface circuits.

Key words: radiation-hardening, triple modular redundancy, interface circuit