关键词: 流水线-逐次逼近型模数转换器, 多比较器结构, 电容型数模转换器

Abstract: A14-bit pipelined-successive approximation analog-to-digital converter (Pipelined-SAR ADC) based on a 22 nm FDSOI CMOS process is presented. The proposed Pipelined-SAR ADC employs a multi-comparator structure and a capacitive digital-to-analog converter (CDAC) in each stage to achieve the compromise between speed and performance. A dynamic amplifier structure with small noise is used between the adjacent two stages, and the influence of the comparator offset voltage on the ADC performance is eliminated by adding one bit redundant bit each in the latter three stages. The pre-simulation results show that when the power supply voltage is 0.8 V, the sampling rate is 1 GSample/s, the input signal frequency is about 103.52 MHz, and the swing is 1.6 V, the effective number of bits (ENOB) of the ADC is 12.16 bits, the signal-to-noise distortion ratio (SNDR) is 74.98 dB, the spurious-free dynamic range (SFDR) is 86.58 dB, the total power consumption is about 75mW, and the area is 0.1849 mm².

Key words: Pipelined-SAR ADC, multi-comparator structure, CDAC