关键词: 锁相环, 负反馈电荷泵, 预充电环形振荡器

Abstract: Aiming at the problems of poor jitter performance of phase-locked loops in double-data rate synchronous dynamic random access memories, a low-jitter phase-locked loop is designed based on the 55 nm CMOS process. A charge pump controlled by negative feedback proportional integration structure is used to obtain good jitter performance and achieve fast lock-up, and the ring oscillator is pre-charged with a pseudo-differential structure to improve the clock flipping speed. The post-simulation results show that under the condition of 2.5 V power supply, the phase-locked loop can be locked at 3.2 GHz in 2 μs, and its phase noise is about -96.2 dBc/Hz@1 MHz. The chip test results show that the output clock cycle jitter is -27.7-23.2 ps.

Key words: phase-locked loop, negative feedback charge pump, pre-charge ring oscillator