中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2020, Vol. 20 ›› Issue (7): 070303 . doi: 10.16257/j.cnki.1681-1070.2020.0704

• 电路设计 • 上一篇    下一篇

基于锁存器实现串并转换电路的方法

项欣1,彭析竹1,2   

  1. 1.电子科技大学,成都 610054;2.电子科技大学广东电子信息工程研究院,广东东莞 523808
  • 接受日期:2020-03-10 发布日期:2020-03-23
  • 作者简介:项 欣(1993—),男,湖北孝感人,硕士研究生,现从事数模混合电路系统领域的研究。

A Method of a Serial-to-Parallel Interface Conversion Circuit Based on Latches

XIANG Xin1, PENG Xizhu1,2   

  1. 1.University of Electronic Science and Technology of China, Chengdu610054,China; 2.Institute of Electronic and Information Engineering of UESTC in Guangdong,Dongguan523808,China
  • Accepted:2020-03-10 Published:2020-03-23

摘要: 介绍了一种基于锁存器的串行数据转并行数据的接口转换电路的设计方法。串并转换电路由采样信号发生器和并行锁存器两部分组成。采样信号发生器用于将时钟转换为一个个和时钟信号边沿对齐的小脉冲,脉冲宽度为时钟周期的一半;并行锁存器是由若干个锁存器并行而成,锁存器数据输入端连接在一起,由采样脉冲控制锁存器对串行输入数据依次进行采样。数据存储在锁存器中不会丢失,直到下一次采样新的数据写入,因此有足够的时序冗余来保证数据的正确输出。最后对电路的功能进行了仿真验真。

关键词: 串并转换, 锁存器, 脉冲采样

Abstract: A method of a serial-to-parallel interface conversion circuit based on latches is introduced in this article. The serial-to-parallel conversion circuit consists of two parts: sampling signals generator and parallel latches. The sampling signals generator is used to convert the clock into small pulses aligned with clock edges. The pulse width is half of the clock period. The parallel latch is made up of several latches in parallel with same data input shared. The serial input data is sequentially sampled by latches which are controlled by sampling pulses. Data stored in the latch will not get lost until the next pulse when new data is coming, so there is enough timing redundancy to ensure the correct output of the data. The functions of the circuit were simulated and verified.

Key words: serial-to-parallel interface, latch, pulse sampling

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