中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

导航

电子与封装 ›› 2024, Vol. 24 ›› Issue (6): 060112 . doi: 10.16257/j.cnki.1681-1070.2024.0143

所属专题: 硅通孔三维互连与集成技术

• “硅通孔三维互连与集成技术”专题 • 上一篇    下一篇

三维异构集成的发展与挑战

马力,项敏,吴婷   

  1. 通富微电子股份有限公司,江苏 南通 226000
  • 收稿日期:2024-04-26 出版日期:2024-06-25 发布日期:2024-06-25
  • 作者简介:马力(1984—),男,江苏昆山人,博士,通富微电子股份有限公司先进封装技术总监,主要研究方向为Chiplet先进封装。

Developments and Challenges of 3D Heterogeneous Integration

MA Li, XIANG Min, WU Ting   

  1. TongFu Microelectronics Co., Ltd., Nantong 226000, China
  • Received:2024-04-26 Online:2024-06-25 Published:2024-06-25

摘要: 三维异构集成技术带动着半导体技术的变革,用封装技术上的创新来突破制程工艺逼近极限带来的限制,是未来半导体行业内的关键技术。三维异构集成技术中的关键技术包括实现信号传输和互连的硅通孔/玻璃通孔技术、再布线层技术以及微凸点技术,不同关键技术相互融合、共同助力三维异构集成技术的发展。芯片间高效且可靠的通信互联推动着三维异构集成技术的发展,现阶段并行互联接口应用更为广泛。异构集成互联接口本质上并无优劣之分,应以是否满足应用需求作为判断的唯一标准。详述了三维异构集成技术在光电集成芯片及封装天线方面的最新进展。总结了目前三维异构集成发展所面临的协同设计挑战,从芯片封装设计和协同建模仿真等方面进行了概述。建议未来将机器学习、数字孪生等技术与三维异构集成封装相结合,注重系统级优化以及协同设计的发展,实现更加高效的平台预测。

关键词: 三维异构集成, 微凸点, 互联接口, 芯片封装设计

Abstract: 3D heterogeneous integration technology is a key technology for the future semiconductor industry as it drives the change of semiconductor technology and breaks through the limitations imposed by the approaching limits of the manufacturing process with innovations in packaging technology. Key technologies in 3D heterogeneous integration technology include silicon-through-via/glass-through-via technology for signal transmission and interconnection, redistribution layer technology and micro-bump technology, which are integrated to facilitate the development of 3D heterogeneous integration technology. Efficient and reliable communication interconnection between chips is driving the development of 3D heterogeneous integration technology, and parallel interconnect interfaces are widely used at present. Interconnect interfaces for heterogeneous integration are not inherently superior or inferior, and should be judged solely on the basis of whether or not they meet the application requirements. The latest advances in 3D heterogeneous integration technology in optoelectronic integrated technology and antenna in package are described in detail. The co-design challenges faced by the development of 3D heterogeneous integration are summarized and overviewed in terms of chip packaging design and co-modeling simulation. It is proposed to combine machine learning, digital twin and other technologies with 3D heterogeneous integration packaging in the future, focusing on the development of system-level optimization as well as co-design development to achieve more efficient platform prediction.

Key words: 3D heterogeneous integration, micro-bump, interconnection interface, chip packaging design

中图分类号: