集成电路互连微纳米尺度硅通孔技术进展*

doi:10.16257/j.cnki.1681-1070.2024.0144

摘要/Abstract

摘要： 集成电路互连微纳米尺度硅通孔（TSV）技术已成为推动芯片在“后摩尔时代”持续向高算力发展的关键。通过引入微纳米尺度高深宽比TSV结构，2.5D/3D集成技术得以实现更高密度、更高性能的三维互连。同时，采用纳米TSV技术实现集成电路背面供电，可有效解决当前信号网络与供电网络之间布线资源冲突的瓶颈问题，提高供电效率和整体性能。随着材料工艺和设备技术的不断创新，微纳米尺度TSV技术在一些领域取得了显著进展，为未来高性能、低功耗集成电路的发展提供了重要支持。综述了目前业界主流的微纳米尺度TSV技术，并对其结构特点和关键技术进行了分析和总结，同时探讨了TSV技术的发展趋势及挑战。

关键词: 先进互连技术, 2.5D/3D芯粒集成, 背面供电, 高深宽比TSV

Abstract: The integrated circuit interconnecting micro- and nano-scale through silicon via (TSV) technology has become the key to driving chips to sustained high-computing power in the post-Moore's Law era. By introducing micro- and nano-scale high depth-to-width ratio TSV structures, the 2.5D/3D integration technology facilitates higher density, higher performance 3D interconnects. At the same time, the implementation of nano-scale TSV technology for backside power delivery in integrated circuits can effectively solve the bottleneck caused by wiring resource conflict between current signal and power delivery networks, and improve the power efficiency and overall performance. With continual innovations in material processes and equipment technologies, micro- and nano-scale TSV technology has made significant progress in some areas, offering critical support for the development of future high-performance, low-power integrated circuits. The current mainstream micro- and nano-scale TSV technologies in the industry are reviewed, and their structural characteristics and key technologies are analyzed and summarized, while the development trends and challenges of TSV technologies are discussed.

Key words: advanced interconnecting technology, 2.5D/3D Chiplet integration, backside power delivery, high depth-to-width ratio TSV

中图分类号:

TN305.94

黎科,张鑫硕,夏启飞,钟毅,于大全. 集成电路互连微纳米尺度硅通孔技术进展^*[J]. 电子与封装, 2024, 24(6): 060111 .

LI Ke, ZHANG Xinshuo, XIA Qifei, ZHONG Yi, YU Daquan. Advances in Micro- and Nano-Scale Through-Silicon-Via Technology for Integrated Circuits Interconnecting[J]. Electronics & Packaging, 2024, 24(6): 060111 .

参考文献

[1] SU L S, NAFFZIGER S. 1.1 innovation for the next decade of compute efficiency[C]// 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023: 8-12.
[2] DATTA S, CHAKRABORTY W, RADOSAVLJEVIC M. Toward attojoule switching energy in logic transistors[J]. Science, 2022, 378(6621): 733-740.
[3] LAU J H. Recent advances and trends in advanced packaging[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(2): 228-252.
[4] BHATTACHARYA S, LIM T G, HO D, et al. Advanced system in package enabled by wafer level heterogeneous integration of chiplets[C]// 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022.
[5] 集成芯片前沿技术科学基础专家组. 集成芯片与芯粒技术白皮书[EB/OL]. [2024-4-20]. https://www.gitlink.org.cn/zone/iChips/source/12.
[6] 于大全. 硅通孔三维封装技术[M]. 北京: 电子工业出版社, 2021.
[7] NVIDIA’s new generation graphics processing unit (GPU) with TSMC CoWoS, 40 GB Samsung HBM2, 2.5D and 3D packaging[EB/OL]. [2024-4-15]. https://www.yolegroup.com.
[8] VELOSO A, VERMEERSCH B, CHEN R, et al. Backside power delivery: Game changer and key enabler of advanced logic scaling and new STCO opportunities[C]// 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023: 1-4.
[9] JOURDAIN A, SCHLEICHER F, DE VOS J, et al. Extreme Wafer thinning and nano-TSV processing for 3D heterogeneous integration[C]// 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020: 42-48.
[10] Backside power delivery[EB/OL]. [2024-4-15]. https://www.imec.be/nl.
[11] JOURDAIN A, STUCCHI M, PLAS G V D, et al. Buried power rails and nano-scale TSV: Technology boosters for backside power delivery network and 3D heterogeneous integration[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2022: 1531-1538.
[12] RADOSAVLJEVI? M, HUANG C Y, GALATAGE R, et al. Demonstration of a stacked CMOS inverter at 60nm gate pitch with power via and direct backside device contacts[C]// 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023: 1-4.
[13] Packaging Integration[EB/OL]. [2024-5-20]. https://irds.ieee.org/.
[14] CROES K, DE MESSEMAEKER J, LI Y L, et al. Reliability challenges related to TSV integration and 3-D stacking[J]. IEEE Design & Test, 2016, 33(3): 37-45.
[15] Through silicon vias (TSV)[EB/OL]. [2024-4-11]. https://www.appliedmaterials.com/us/en/semiconductor/markets-and-
inflections/heterogeneous-integration/tsv.html.
[16] AMT TSV pattern-process steps[EB/OL]. [2024-4-11]. https://amti.co.jp/1078/.
[17] Heterogeneous integration rescuing moore’s law[EB/OL]. [2024-4-10] https://eri-summit. darpa.mil/docs/ 20180724_1030_ CHIPS .pdf.
[18] SOURIAU J C, LIGNIER O, CHARRIER M, et al. Wafer level processing of 3D system in package for RF and data application[C]// Proceedings Electronic Components and Technology, 2005, Lake Buena Vista, FL, USA, 2005: 356-361.
[19] SELVANAYAGAM C S, LAU J H, ZHANG X W, et al. Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps[J]. IEEE Transactions on Advanced Packaging, 2009, 32(4): 720-728.
[20] KHAN N, RAO V S, LIM S, et al. Development of 3-D silicon module with TSV for system in packaging[J]. IEEE Transactions on Components and Packaging Technologies, 2010, 33(1): 3-9.
[21] ZHAN C J, TZENG P J, LAU J H, et al. Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP[C]// 2012 IEEE 62nd Electronic Components and Technology Conference, San Diego, CA, USA, 2012: 548-554.
[22] CHIEN H C, CHAO Y L, LAU J H, et al. A thermal performance measurement method for blind through silicon vias (TSVs) in a 300mm wafer[C]// 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, USA, 2011: 1204-1210.
[23] SIRBU B, EICHHAMMER Y, OPPERMANN H, et al. 3D silicon photonics interposer for Tb/s optical interconnects in data centers with double-side assembled active components and integrated optical and electrical through silicon via on SOI[C]// 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2019: 1052-1059.
[24] BANIJAMALI B, RAMALINGAM S, NAGARAJAN K, et al. Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA[C]// 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, USA, 2011: 285-290.
[25] HOU S Y, HSIA H, TSAI C H, et al. Integrated deep trench capacitor in Si interposer for CoWoS heterogeneous integration[C]// 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019.
[26] HUANG P K, LU C Y, WEI W H, et al. Wafer level system integration of the fifth generation CoWoS?-S with high performance Si interposer at 2500 mm2[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021: 101-104.
[27] Highlights of the TSMC Technology Symposium[EB/OL]. [2024-3-11]. https://semiwiki.com/ semiconductor-manufacturers/tsmc/290560-highlights-of- the- tsmc technology -symposium-part-2.
[28] LAU J H. Advanced packaging[M]. Berlin: Springer, 2021.
[29] HOU S Y, CHEN W C, HU C, et al. Wafer-level integration of an advanced logic-memory system through the second-generation CoWoS technology[J]. IEEE Transactions on Electron Devices, 2017, 64(10): 4071-4077.
[30] LIN F, KEETH B. Memory interface design for hybrid memory cube (HMC)[C]// 2016 IEEE Workshop on Microelectronics and Electron Devices (WMED), Boise, ID, USA, 2016: 1-5.
[31] LEE J C, KIM J, KIM K W, et al. High bandwidth memory(HBM) with TSV technique[C]// 2016 International SoC Design Conference (ISOCC), Jeju, Korea (South), 2016: 181-182.
[32] LEE D U, KIM K W, KIM K W, et al. 25.2 A 1.2V 8 Gb 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[C]// 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014: 432-433.
[33] LAU J H. Recent advances and trends in chiplet design and heterogeneous integration packaging[J]. Journal of Electronic Packaging, 2024, 146(1): 010801.
[34] HUYLENBROECK S V, VOS J D, EL-MEKKI Z, et al. A highly reliable 1.4 μm pitch via-last TSV module for wafer-to-wafer hybrid bonded 3D-SOC systems[C]// 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2019: 1035-1040.
[35] MOON K I, SON H Y, LEE K. Advanced packaging technologies in memory applications for future generative AI era[C]// 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023: 1-4.
[36] Embrace limitless challenges to strengthen advanced packaging technology[EB/OL]. [2024-5-23]. https://news.skhynix.com/.
[37] BEYNE E, JOURDAIN A, BEYER G. Nano-through silicon vias (nTSV) for backside power delivery networks (BSPDN)[C]// 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023: 1-2.
[38] 钟毅, 江小帆, 喻甜, 等. 芯片三维互连技术及异质集成研究进展 [J]. 电子与封装, 2023, 23(3): 030102.
[39] HUYLENBROECK S V, LI Y L, HEYLEN N, et al. Advanced metallization scheme for 3×50 μm via middle TSV and beyond[C]// 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2015: 66-72.
[40] KILLGE S, BARTUSSECK I, JUNIGE M, et al. 3D system integration on 300 mm wafer level: High-aspect-ratio TSVs with ruthenium seed layer by thermal ALD and subsequent copper electroplating[J]. Microelectronic Engineering, 2019, 205: 20-25.
[41] ZHANG Z Y, CHEN Z M, YANG B Y, et al. Enabling low-k liner in ultra-high aspect ratio TSVs by the timing of vacuum treatment in the vacuum-assisted spin-coating technique[C]// 2023 24th International Conference on Electronic Packaging Technology (ICEPT), Shihezi, China, 2023: 1-4.
[42] ZHANG Z Y, DING Y T, XIAO L, et al. Enabling continuous Cu seed layer for deep through-silicon-vias with high aspect ratio by sequential sputtering and electroless plating[J]. IEEE Electron Device Letters, 2021, 42(10): 1520-1523.
[43] KOYANAGI M, NAKAMURA T, YAMADA Y, et al. Three-dimensional integration technology based on wafer bonding with vertical buried interconnections[J]. IEEE Transactions on Electron Devices, 2006, 53(11): 2799-2808.
[44] IGARASHI Y, MOROOKA T, YAMADA Y, et al. Filling of tungsten into deep trench using time-modulation CVD method[C]// Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials, Diamond Hotel, Tokyo, Japan, 2001.
[45] FUKUSHIMA T, SAKUYAMA S, TAKAHASHI M, et al. Integration of damage-less probe cards using nano-TSV technology for microbumped wafer testing[C]// 2021 IEEE International 3D Systems Integration Conference (3DIC), Raleigh, NC, USA, 2021: 1-4.
[46] WANG M Y, LI K, BAO S C, et al. Completely filling of through-silicon-vias with high aspect ratio by high cavity physical vapor deposition and electroplating[C]// 2023 24th International Conference on Electronic Packaging Technology (ICEPT), Shihezi, China, 2023: 1-4.
[47] WU L C, LIU Z Y, WANG J. A stress evaluation approach for the silicon with nano-TSVs by Raman spectroscopy[C]// 2023 24th International Conference on Electronic Packaging Technology (ICEPT), Shihezi, China, 2023: 1-5.
[48] WANG Y, LIU Z Y, LI J Z, et al. Etching scallop-less nano-TSV with F/O coupling plasma[C]// 2023 24th International Conference on Electronic Packaging Technology (ICEPT), Shihezi, China, 2023: 1-4.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

集成电路互连微纳米尺度硅通孔技术进展^*

Advances in Micro- and Nano-Scale Through-Silicon-Via Technology for Integrated Circuits Interconnecting

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 1

编辑推荐

Metrics

本文评价