先进封装驱动下的片上互连技术发展态势研究

doi:10.16257/j.cnki.1681-1070.2025.0135

摘要/Abstract

摘要： 随着登纳德缩放定律的失效以及摩尔定律的减缓，芯片性能的提升越来越依赖于多核架构。片上互连技术已经成为决定处理器性能的关键因素。片上网络技术和先进封装技术为处理器核心数量的规模化增长提供了必要的前提条件。然而，受先进封装技术的驱动，片上互连的拓扑结构正经历从二维向三维的转变，这一变化导致互连结构复杂度提升，互连场景也日趋多样化。传统的基于电信号的有线互连技术已经显示出其局限性，而光互连和无线互连等前沿技术则有望在未来高性能计算等领域中得到应用，成为现有互连方式的有力补充。

关键词: 片上网络, 3D封装, 光互连, 无线互连

Abstract: With the failure of Dennard scaling and the slowdown of Moore's Law, chip performance enhancement is increasingly reliant on multi-core architectures. On-chip interconnect technology has become a core factor in determining processor performance. Network-on-chip technology and advanced packaging technology provide the essential prerequisites for the large-scale increase in the number of processor cores. However, driven by advanced packaging technology, the topology of on-chip interconnects is shifting from two-dimensional to three-dimensional, making the interconnect structure more complex and the interconnect scenarios more diversified. Traditional wired interconnects based on electrical signals have shown inherent limitations. Optical interconnects and wireless interconnects, as emerging technologies, have the potential to be applied in future high-performance computing and other scenarios, becoming a powerful supplement to existing interconnect methods.

Key words: network-on-chip, 3D packaging, optical interconnect, wireless interconnect

中图分类号:

王翰华，崔忠杰. 先进封装驱动下的片上互连技术发展态势研究[J]. 电子与封装, 2025, 25(12): 120203 .

WANG Hanhua, CUI Zhongjie. Research on the Development Trends of On-Chip Interconnect Technologies Driven by Advanced Packaging[J]. Electronics & Packaging, 2025, 25(12): 120203 .

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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊