3D异构集成的多层级协同仿真

doi:10.16257/j.cnki.1681-1070.2021.1010

摘要/Abstract

摘要： 3D异构集成技术是未来电子行业的关键技术，促使电子系统朝着高性能、低延迟、小尺寸、轻质量、低功耗和低成本的方向发展。然而，随着信号传输速率和带宽的提高，异构集成系统各层级之间的相互干扰愈发显著，亟需多层级的协同仿真技术来捕获这种干扰，从而避免多次迭代造成的经济和时间成本增加。多层级协同建模和仿真技术可实现跨芯片-封装-系统领域的多层级协同开发以及跨电学、热学、机械学的多物理场协同分析，是实现3D异构集成的重要保障。介绍了异构集成协同仿真的基本概念，详述了协同仿真关键技术的发展和研究现状，总结了协同仿真的挑战和发展趋势。

关键词: 3D异构集成, 多层级协同仿真, 参数提取, 信号完整性, 热力协同分析

Abstract: 3D heterogeneous integration is the key technology in the future electronic industry, which promotes the electronic systems to higher performance, lower signal delay, smaller size, lighter weight, lower power dissipation and lower cost. However, the mutual interferences between multi-levels in heterogeneous integration are becoming more and more serious. Multi-level co-simulation technology is needed to capture these interferences, thus enormous economic and time costs caused by multiple iterations can be avoided. Co-simulation and modeling technology can realize the co-analysis referring to die-package-system levels and electromagnetic, thermal and mechanical fields, and becoming a significant factor to guarantee the implementation of 3D heterogeneous integration. Basic concepts of co-simulation technology for 3D heterogeneous integration are introduced. And the developments and current situations of some key technologies such as modeling and parameter extraction, power distribution network (PDN) analysis and thermal-mechanical co-analysis are demonstrated in detail. The challenges and development trends in co-simulation technology are proposed.

Key words: 3Dheterogeneousintegration, multi-levelco-simulation, parameterextraction, signalintegrity, thermal-mechanicalco-analysis

中图分类号:

TN405.97

曾燕萍, 张景辉, 朱旻琦, 顾林. 3D异构集成的多层级协同仿真[J]. 电子与封装, 2021, 21(10): 100105 .

ZENG Yanping, ZHANG Jinghui, ZHU Minqi, GU Lin. Multi-Level Co-Simulation of3D Heterogeneous Integration[J]. Electronics & Packaging, 2021, 21(10): 100105 .

参考文献

[1] BAILEY C, FAN X J, BOTTOMS W R, et al. Heterogeneous integration roadmap[EB/OL]. (2019-09-19) [2021-05-06]. http://eps.ieee.org/hir.
[2] TIMOTHY M H, JEFFREY C D, BOOZ A H. Heterogeneous and 3D integration at DARPA[C]// 2019 International 3D System Integration Conference(3DIC), 2019: 1-4.
[3] ARDEN W. More-than-Moore white paper, ITRS roadmap[EB/OL]. [2021-05-06]. http://www.itrs2.net/uploads/4/9/7/7/49775221/irc-itrsmtm-v2_3.pdf.
[4] RADOJCIC R. More-than-Moore 2.5D and 3D SiP integration[M]. West Berlin: Springer Publishing Company, 2017: 13-25.
[5] GARROU P. DARPA envisions CHIPS as new approach to chip design and manufacturing[EB/OL]. (2018-10-17)[2021-04-30].https://www.3dincites.com/2018/10/iftle-396-darpa-envisions-chips-as-new-approach-to-chip-design-and-manufacturing/
[6] https://www.intel.com/content/www/us/en/architecture-and-technology/programmable/heterogeneousintegration/overview.html
[7] fraunhofer-iis, electrinica-2018[EB/OL]. (2018-11-13)[2021-05-06]. https://www.iis.fraunhofer.de/en/muv/2018/electrinica-2018.html
[8] BHATTACHARYA R, LOHANI J, GUPTA A, et al. Enabling chip, package and PCB system co-design and analysis in a heterogeneous integration environment-An EDA approach[C]// 2019 IEEE 20th Wireless and Microwave Technology Conference (WAMICON), 2019: 1-4.
[9] HARB S, EISENSTADT W. Thermal evaluation of TSVs in 3D-integration technology[C]// 2019 IEEE 21st Electronics Packaging Technology Conference (EPTC), 2019: 1-4.
[10] JANG J G, SUK K L, LEE S H. Advanced RDL interposer PKG technology for heterogenous integration[C]// 2020 International Wafer Level Packaging Conference (IWLPC), 2020: 1-5.
[11] CHOI W S, KWAK S K, KIM D Y. The SI/PI modeling and measurement of memory system by probing on top of DRAM package[C]// DesignCon, 2020.
[12] HOSSEN M O, CHAVA B, BAKIR M S. Power delivery network (PDN) modeling for backside-PDN configurations with buried power rails and μTSVs[J]. IEEE Transactions on Electron Devices, 67(1): 11-17, 2020.
[13] Kim J, Rahman N M, Dolatsara M A, et al. Silicon vs organic interposer: PPA and reliability tradeoffs in heterogeneous 2.5D chiplet integration[C]// 2020 IEEE 38th International Conference on Computer Design (ICCD), 2020: 80-87.
[14] SHIUE G, AINé S. Rapid electro-thermal modeling for 3D integration using circuit simulation techniques[C]// 2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), 2018:63-63.
[15] LI Y S, LI E P, YU H, et al. Machine learning for 3D-IC electric-thermal simulation and Management[C]// 2018 IEEE International Conference on Computational Electromagnetics (ICCEM), 2018: 1-3.
[16] YAN X, ZHANG, ZHOU L. Calculations of temperature distributions for power MMICs in 3-D packages[C]// 2020 International Conference on Microwave and Millimeter Wave Technology (ICMMT), 2020: 1-3.
[17] CHEN Z. A general co-design approach to multi-level package modeling based on individual single-level package full-wave S-parameter modeling including signal and power/ground ports[C]// 2012 Electronic Components and Technology Conference (ECTC), 2012: 1687-1694.
[18] DARRYL K, TAIGON S, SUNG K L. 3D IC-package-board co-analysis using 3D EM simulation for mobile applications[C]// 2013 Electronic Components & Technology Conference, 2013: 2113-2120.
[19] 曾燕萍, 张景辉, 王梦雅, 等. DDR3堆叠键合组件的信号完整性分析与优化[J]. 电子与封装, 2020, 20(12): 120201.
[20] OYMAN S. Electromagnetic wave propagation equations in 2D by finite difference method: mathematical case[C]// 2019 3rd International Symposium on Multidisciplinary Studies and Innovative Technologies (ISMSIT), Ankara, Turkey, 2019: 1-5.
[21] DEMENKO A, SYKULSKI J K. Analogies between finite-difference and finite-element methods for scalar and vector potential formulations in magnetic field calculations[J]. IEEE Transactions on Magnetics, 2016, 52(6): 1-6.
[22] JIA P, HU J, ZHANG R, et al. Computations of electromagnetic wave scattering using FEM-BEM-DDM with H-matrices[C]// 2017 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting, USA, 2017: 1335-1336.
[23] YU W, WANG X. Advanced field-solver techniques for RC extraction of integrated circuits[M]. Springer Science & Business, 2014: 73-86.
[24] YU W J, SONG M Y, YANG M. Advancements and challenges on parasitic extraction for advanced process technologies[C]// 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021: 841-846.
[25] WANG M Y, QIAN C, Yucel A C, et al. An FFT-accelerated and tucker-enhanced inductance extraction for voxelized superconducting structures[C]// 2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting, Montreal, QC, Canada, 2020: 1049-1050.
[26] LIU Q, SHAO Z, ZHANG Y, et al. A fast and accurate method for bond wires inductances extraction based on machine learning strategy[C]// 2020 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), China, 2020: 1-3.
[27] 姜立军，姚赫明，张欢欢，等. 开发EMC/SI/PI 的机器学习CEM方法[J]. 安全与电磁兼容, 2020（5）: 9-15.
[28] PENG Y, PETRANOVIC D, LIM S K. Chip/package co-analysis and inductance extraction for fan-out wafer-level-packaging[C]// 2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, USA, 2017: 1-3.
[29] 陈思远，范鑫，蒋剑飞，等. 一种TSV阵列的串扰抑制设计方法[J].微电子学与计算机, 2018(7): 19-23.
[30] QU C B, DING R X, ZHU Z M. High-frequency electrical modeling and characterization of differential TSVs for 3-D integration applications[J]. MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2017, 27(8): 721-723.
[31] LIU X X, ZHU Z M, YANG Y T, et al. Electrical modeling and analysis of differential dielectric-cavity through-silicon-via array[J]. MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2017, 27(7): 618-620.
[32] JIANG X H, SHI H. Effective die-package-PCB co-design methodology and its deployment in 10 Gbpsserial link transceiver FPGA packages[C]// 2009 IEEE MTT-S International Microwave Symposium Digest, 2009: 793-796.
[33] ZHANG Y, Bakir M S. Integrated thermal and power delivery network co-simulation framework for single-die and multi-die assemblies[J]. IEEE Trans. Compon., Packag., Manuf. Technol., 2017,7(3): 434-443.
[34] ZHANG Y, HOSSEN M O, BAKIR M S. Power delivery network benchmarking for interposer and bridge-chip-based 2.5-D integration[J]. IEEE Electron Device Letter, 2018, 39(1): 99-102.
[35] HOSSEN M O, ZHANG Y, BAKIR M S. Thermal-power delivery network co-analysis for multi-die integration[C]// IEEE 27th Conf. Elect. Perform. Electron. Packag. Syst. (EPEPS), Oct. 2018: 155-157.
[36] 秦海潮，阎照文，苏东林，等. 三维TSV集成电路电磁敏感性分析方法[J]. 北京航空航天大学学报, 2017,43(12): 2406-2415.
[37] PENG Y, SONG T, PETRANOVIC D, et al. Silicon effect-aware full-chip extraction and mitigation of TSV-to-TSV coupling[J]. IEEE Transition of Computer-Aided Design for Integration Circuits System, 2014,33(12): 1900-1913.
[38] 孟真，刘谋，张兴成，等. TSV封装中阻抗不连续差分互连结构宽频寄生参数建模研究[J]. 微电子学与计算机, 2017,34(08): 6-12.
[39] PANT S. Design and analysis of power distribution networks in VLSI circuits[D]. Doctoral Dissertation, State of Michigan, University of Michigan, 2007.
[40] YEUNG A, PARTOVI H, HARVARD Q, et al. A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology[C]// International Solid-State Circuit Conference (ISSCC), 2014: 110-111.
[41] 张诚，周倩蓉，曾燕萍，等. 本征模在电源完整性分析中的应用[J]. 电子与封装, 2020, 20(3): 030305.
[42] SHIDHARTHA D, PAUL W, DAVID B. Modeling and characterization of the system-level power delivery network for a dual-core ARM Cortex-A57 cluster in 28 nm CMOS[C]// Symposium on Low Power Electronics and Design, 2015: 146-151.
[43] 苏浩航. 基于混合仿真对高速电路电源网络的优化设计[J]. 航天返回与遥感, 2017, 38(5):50-56.
[44] SMITH L, SUN S H, BOYLE P, et al. System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing[C]// IEEE 2009 Custom Intergrated Circuits Conference (CICC), 2009: 621-628.
[45] 刘洋，夏建强，初秀琴. 利用有效去耦上升时间选择去耦电容的方法[J]. 西安电子科技大学学报. 2018, 45(04): 45-51.
[46] HASHEMI A, CHEN G, KANG H S. Signal and power integrity co-simulation for high-density heterogenous multi-die design[C]// DesignCon, 2020.
[47] CHANDRASEKAR K, ATTA E, PAWASKAR P. EDA flows and modeling approaches to study analog/digital coupling[C]// DesignCon, 2020.
[48] MOON S, PRSTIC S, CHIU C. Thermal management of a stacked-die package in a handheld electronic device using passive solutions[J]. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2008, 31(1): 791-797.
[49] 何成. 典型封装芯片的热阻网络模型研究[D]. 西安: 西安电子科技大学, 2014．
[50] 申海东，张泽，陈科雯，等. 基于双热阻模型的典型芯片封装热分析及评估方法[J]. 装备环境工程, 2018, 15(7): 10-14.
[51] 李逵，张庆学，张欲欣，等. TSV结构SiP模块的等效建模仿真与热阻测试[J]. 半导体检测与设备, 2020,45(12): 982-987.
[52] KONG L S, YAO Q B, LV X R, et al. Submodelling method for modelling and simulation of high density electronic assemblies[J]. Journal of Physics, 2020: 1-10.
[53] 袁伟星，曾燕萍，张琦，等. 基于多尺度等效模型的SiP热分析及散热优化[J]. 电子与封装，2021, 21(8): 080201.
[54] WANG H, LI D, Gupta A X. Composable thermal modeling and characterization for fast temperature estimation[C]// IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010.
[55] SU Y F, YANG F, ZENG X. AMOR: An efficient aggregating based model order reduction method for many-terminal interconnect circuits[C]// IEEE/ACM Design Automation Conference(DAC), 2012.
[56] DONG X J, GRIFFO A, WANG J B. Fast simulation of transient temperature distributions in power modules using multiparameter model reduction [J]. The Journal of Engineering, 2019(17): 3603-3608.
[57] 严星. 功率MMIC三维异构集成与封装的热分析与仿真研究[D]. 上海: 上海交通大学, 2019.
[58] 王金兰，仝良玉，刘培生，等. 一种多芯片封装(MCP)的热仿真设计[J]. 计算机工程与科学，2012，34(4):28-31.
[59] 芮喜. 多芯片组件的扩展热阻与热耦合效应研究[D]. 西安：西安电子科技大学，2015.
[60] WU Q S, LI G Y, ZHOU B, et al. Research on vibration reliability of system in package[J]. 20th International Conference on Electronic Packaging Technology, 2019.
[61] BORISKOV P, ERSHOVA N, PUTROLAYNEN V, et al. Temperature simulation of system-in-package produced with hybrid chip mounting technology[J]. International Conference on Information Processing and Control Engineering, 2019.
[62] HUANG J Y, CAO Y, GAO C. Vulnerability analysis of system-in-package based on reliability enhancement testing simulation[J]. 2nd International Conference on Safety Produce Informatization (IICSPI), 2019, 639-644.
[63] 张琦，曾燕萍，袁伟星，等. 大功率高性能SiP的电热耦合分析[J]. 电子与封装，2021, 2021(8): 080403.
[64] 韩志康，王勇勇，杨勋勇，等. 多层芯片键合界面的可靠性仿真分析[J]. 传感器与微系统, 2020, 39(3): 50-56.
[65] POGUDKIN A V, BELYAKOV I A, VERTYANOV D V, et al. Research of reconstructed wafer surface planarity on the metal-compound-silicon boundary for multi-chip module with embedded dies[C]// 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, 2019: 2008-2012.
[66] 张墅野，鲍天宇，修子扬. 三维封装电迁移Cu互连线的多物理场模拟仿真[J]. 材料导报, 2021, 35(2): 02133-02138
[67] 李梦琳，张欲欣，肖泽平. 2.5D TSV封装结构热应力可靠性研究[J]. 电子工艺技术, 2020, 41(3): 153-155.
[68] 罗江波. 高性能硅转接板的系统设计及集成制造方法研究[D]. 上海: 上海交通大学, 2019.
[69] 陈亚秋. 基于ECPT的焊点可靠性评估方法研究[D]. 成都:电子科技大学, 2018.
[70] LI Y Y, DONG D, WANG H. Simulation and fatigue damage prediction for board level CBGA solder joint of LTCC-based SiP module under random vibration loading[C]// 20th International Conference on Electronic Packaging Technology, 2019.
[71] 焦鸿浩. 多物理场载荷下电子封装板级焊点仿真研究[D]. 黑龙江: 哈尔滨理工大学, 2019.
[72] MA Y Y, TALLEDO J, LUAN J E. Thermal cycling durability assessment and enhancement of FBGA package for automotive applications[C]// 20th International Conference on Electronic Packaging Technology, 2019.
[73] 张振越，李祝安，王剑峰，等. 倒装焊封装器件热仿真校准技术研究[J]. 计量与测试技术, 2020, 38(5): 103-106.
[74] 石潇. 覆铜型式对PCB板上电子元件热布局优化效果的影响研究[D]. 西安: 长安大学, 2018.
[75] 张琦. 基于交错堆叠DDR模组的结温预测与优化研究[D]. 南京: 南京邮电大学, 2020.
[76] 王家睿. MCM热布局的模糊遗传算法分析[J]. 科技创新导报, 2019（28）: 111-112.
[77] 杨志清，潘中良. 基于遗传粒子群算法的三维芯片热布局优化[J].电子工艺技术, 2019,40(5): 249-260.
[78] CAI T T, XI W, SUO S L, et al. A multi-chip SiP package design scheme[C]// 2019 IEEE 8th Joint International Information Technology and Artificial Intelligence Conference, 2019, 1889-1893.
[79] KIMMO R, KOEN B, KRISTOFFER A, et al. Multi-physical simulations and modelling of an integrated GaN-on-Si module concept for millimetre-wave communications[C]// 2020 IEEE 70th Electronic Components and Technology Conference, 2020, 1369-1375.
[80] LI Z R, XU G, HUANG XJ, et al. Evaluation method of electronic performance margins for Sip based on field-circuit and multiple physical cooperative simulation[C]// 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC), 2019: 1-6.

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