关键词: FPGA, 逻辑优化, 自动测试, 测试例生成

Abstract: The quality of FPGA supporting software greatly affects the work efficiency of electronic engineering designers. FPGA synthesis is an important part of FPGA design process and the basis for all subsequent work, which greatly affects the effect of FPGA tools. The research of automatic test case generation technology can effectively drive the development of FPGA design tools and improvement the quality. A method for automatically generating test cases is introduced. This method uses controllable injection of "Don’t Cares" or "Redundancy", as well as adjustable input and output parameters and logic levels to generate test cases. The generated test cases can be used to test whether various strategies for logic optimization in FPGA synthesis achieve the expected goals, and assist in optimizing the FPGA synthesis effect.

Key words: FPGA, logicoptimization, automatedtest, testcasegeneration