[1] YANG H S, MALIK R, NARASIMHA S, et al. Dual stress liner fir high performance sub-45 nm gate length SOI CMOS manufacturing[C]// IEDM Tech. Dig. San Francisco CA USA 2004: 1075-1078. [2] SINHA A K, LEVINSTEIN H J, SMITH T E. Thermal stresses and cracking resistance of dielectric films (SiN, Si3N4, and SiO2) on Si substrates[J]. Journal of Applied Physics, 1978, 49(4): 2423-2426. [3] 郭学敏,朱平. 多层薄膜热应力模拟[J]. 应用力学学报,2020, 37(2): 743-749. [4] ITO S, NAMBA H, YAMAGUCHI K, et al. Mechanical stress effect of etch-stop nitride and its impact on deep submicron t ransistor design[C]// IEDM Tech Dig Francisco CA, USA. 2000: 247-250. [5] ARGHAVANI R, XIA L, H M, et al. A reliable and manufacturable method to induce a stress of >1 GPa on a P-channel MOSFET in high volume manufacturing[J]. IEEE Electron Device Letters, 2006, 27(2): 114-116. [6] 王敬轩,商庆杰,杨志. 低压化学气相淀积低应力氮化硅工艺研究[J]. 电子与封装, 2021, 21(8): 080405. [7] LIU L, LIU W G, CAO N, et al. Study on the performance of PECVD silicon nitride thin films[J]. Defence Technology, 2013, 9 (2): 121-126. [8] 汪文君,孙建洁,朱塞宁,等. PECVD法氮化硅薄膜制备的工艺研究[J]. 电子与封装,2013, 13(11): 42-45. [9] 石霞,孙俊峰,顾晓春. SiN介质薄膜内应力的实验研究[J]. 半导体技术,2007, 32(10): 42-45. [10] LEE A S, RAJAGOPALAN, LE M, et a1. Development and characterization of a PECVD silicon nitride for damascene applications[J]. ELECTROCHEM SOC, 2004, 151(1): 7-9. [11] SMITH D L, ALIMONDA A S, CHEN C C, et a1. Mechanism of SiNxHy deposition from NH3-SiH4 plasma[J]. ELECTROCHEM SOC, 1990, 8(3): 551-557. |