中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2022, Vol. 22 ›› Issue (7): 070403 . doi: 10.16257/j.cnki.1681-1070.2022.0710

• 材料、器件与工艺 • 上一篇    下一篇

可变高应力氮化硅薄膜的内应力研究

孙建洁;张可可;陈全胜   

  1. 无锡中微晶园电子有限公司,江苏 无锡 214035
  • 收稿日期:2021-12-21 出版日期:2022-07-28 发布日期:2022-02-21
  • 作者简介:孙建洁(1982—),男,江苏无锡人,本科,工程师,长期从事半导体晶圆制造前道注入和薄膜工艺的研发工作。

Studyof Internal Stress in Variable High Stress SiN Films

SUN Jianjie,ZHANG Keke, CHEN Quansheng   

  1. Wuxi ZhongweiMicrochips Co., Ltd., Wuxi 214035, China
  • Received:2021-12-21 Online:2022-07-28 Published:2022-02-21

摘要: 以互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)器件等比例缩小为动力的硅集成电路技术已迈入纳米级尺寸,并将继续保持对摩尔定律的追求,进一步缩小器件尺寸,以满足芯片高度集成化的要求。目前基于CMOS工艺的应变硅技术受到越来越广泛的应用。氮化硅致应变技术是属于应变硅技术中的一种,该技术工艺流程相对简单,成本较低,仅通过在器件上淀积不同应力的氮化硅薄膜就可达到提高载流子迁移率的效果,因此应用越来越普遍。利用等离子体增强化学气象沉积(Plasma-Enhanced Chemical Vapor Deposition,PECVD)的氮化硅膜,通过适当的工艺条件,可以做到压应力和张应力两种应力的变换,最终可实现在硅片上淀积出应力大于2 GPa的高应力氮化硅膜。

关键词: 应变硅, 氮化硅, 压应力, 张应力

Abstract: Silicon integrated circuit technology driven by the equal scale reduction of CMOS devices has moved into the nano scale, and will continue to maintain the pursuit of Moore's law and further reduce the device size to meet the requirements of highly integrated chips. At present, strained silicon technology based on COMS process is used more and more widely. SiN strain technology is one of the strained silicon technologies. The process of this technology is relatively simple and the cost is low. Only by depositing SiN films with different stresses on devices, carrier mobility can be improved, therefore, it is more and more widely used. By using plasma-enhanced chemical vapor deposition (PECVD) SiN films, the transformation of compressive stress and tensile stress can be achieved through appropriate process conditions, and high stress SiN films with stresses greater than 2 GPa can be deposited on silicon wafers.

Key words: strained silicon, SiN, compressive stress, tensile stress

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