关键词: JTAG接口, 配置码格式, 多工位, 并行工作

Abstract: In recent years, domestic requirements have been put forward for electronic components in application fields such as national defense, and high-performance complex programmable logic devices(CPLDs) designed independently have emerged. These CPLDs need to be tested and selected according to a certain standard process, with program/erase cycles being an important assessment indicator. The shortcomings of usingintegrated development environment and automated testing machine to verify the CPLD program/erase cyclesare described, and a design of CPLD program/erase cycles verification device is proposed. After practical testing, the designed device is stable and reliable, meeting the verification requirements of a large number of devices,and greatly improving the efficiency of CPLD program/erase cycles verification.

Key words: JTAG interface, programming code format, multiple test sites, parallel working