关键词: 乘法器, Booth编码, 部分积, 压缩器

Abstract: In order to improve the performance of the multiplier, a Booth encoder is designed by using the Radix 4 Booth encoding algorithm, and a signed 16 bit multiplier is designed by using the Wallace tree compression structure. A new partial product generator is proposed for the complex process of partial product generation, which simultaneously generates and selects the partial products, and improves the efficiency of the partial product generation. For the waste of resources in the compression process, a partial product advance compressor is proposed to merge certain partial products before entering the compressed tree, reducing the use of compression units. The multiplier logic synthesis is based on 28 nm process. The critical path delay is 0.77 ns, the total area is 937.3 μm², and the power consumption is 935.71 μW, which can better improve the area utilization and computing performance of the multiplier.

Key words: multiplier, Booth encoding, partial product, compressor