中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2018, Vol. 18 ›› Issue (3): 17 -21. doi: 10.16257/j.cnki.1681-1070.2018.0027

• 电路设计 • 上一篇    下一篇

一种低功耗8位300 MS/s异步SAR ADC

钱正,赵新,龚敏,高博,谭萍,王堋钰   

  1. 四川大学物理科学与技术学院,成都 610064
  • 收稿日期:2017-12-02 出版日期:2018-03-20 发布日期:2018-03-20
  • 作者简介:钱正(1993—),男,北京人,四川大学硕士研究生,主要研究方向为模拟集成电路设计。

A Low-power 8-bit 300 MS/s Asynchronous SAR ADC

QIAN Zheng,ZHAO Xin,GONG Min,GAO Bo,TAN Ping,WANG Pengyu   

  1. College of Physical Science and Technology,Sichuan University,Chengdu 610064,China
  • Received:2017-12-02 Online:2018-03-20 Published:2018-03-20

摘要: 设计了一种单循环8位300 MS/s低功耗异步SAR ADC。设计基于内部时钟电路,实现异步算法,使得ADC整体速度得到提升。采用分裂式顶端采样DAC阵列、高速比较器、自举开关以及低功耗动态逻辑单元,使得电路在高速转换下可以保持低功耗。基于SMIC 65 nm工艺实现,在1.2 V电源电压以及300 MS/s的采样频率下,总功耗为0.84 mW。ADC的信噪失真比(SNDR)达到47.9 dB,有效位数(ENOB)达到7.6位,品质因数为16.6 fJ/Conv。

关键词: 高速, 低功耗, SAR ADC, 品质因数

Abstract: A low-energy8-bit 300 MS/s asynchronous SAR ADC is presented.The design based on the internal clock circuit to achieve asynchronous algorithm,which make the overall speed of the ADC is improved.To achieve a high-speed and low-power operation,the design consists of top-plate sampling,high-speed comparator,bootstrapped switch and low-power digital control circuit.Based on the 65 nm CMOS technology,the post-layout simulation results show that at 1.2 V supply and 300 MS/s,the proposed ADC consumes 0.84 mW.Withan ENOB of7.6bit,this results in a FOM of16.6fJ/conv respectively.

Key words: high-speed, low-power, SARADC, FOM

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