Abstract: Since the operational amplifiers in pipeline ADCs are usually designed to meet the speed requirements during the design process, high signal acquisition accuracy is often not achieved, which results in gain errors in the multiplying digital-to-analog converter (MDAC) in the pipelined ADC. A digital background calibration method based on pseudo-random noise injection to calibrate the interstage gain of MDAC is proposed. The calibration algorithm is applied to a pipeline ADC with 12-bit resolution 250 MS/s sampling rate, after calibration, the ADC effective number of bits(ENOB) can reach 11.826 bit, the signal-to-noise ratio (SNDR) can reach 72.95 dB, and the spurious free dynamic range (SFDR) can reach 89.023 dB.

Key words: pipeline ADC, digital calibration, pseudorandom noise