关键词: FPGA, 占空比, 整数半整数分频, 差分

Abstract: In the paper, an FPGA-based frequency dividing circuit is designed. In the design, the FPGA phase-shift clock and flip-flop circuit are used to adjust the duty cycle of clock according to phase relation among phase-shift clocks. The design uses multi-input differential clock latch to achieve the integer/half-integer clock division. And the results are verified by simulations.

Key words: FPGA, duty-cycle, integer or half-integer frequency division, differential circuit