关键词: 变速箱, 标志位控制, 高速串行通信, Serdes, FPGA系统

Abstract: In the paper，a new design of gearbox that adapts the same clock at the both sides instead of involving an extra clock input is presented.It controls the whole process of bit width conversion by counters and produces flag bit to determine the input and output of the gearbox data.The design solves the problem of data repetition and loss during the transmission under fixed baud rate and consequently realizes the perfect conversion between the different bit-wide data.Under the situations when the data bit width are different among modules or IPs，the design is effective in adjusting and matching the data bit widths among modules. The simulation results show that the gearbox completes the data conversion from 66 bits to 64 bits within 32 clock cycles without loss of data rate.

Key words: gearbox, flag bit control, high-speed serial communication, Serdes, FPGA