功率集成器件及其兼容技术的发展*

doi:10.16257/j.cnki.1681-1070.2021.0414

摘要/Abstract

摘要： 功率集成器件在交流转直流（AC/DC）电源转换IC、高压栅驱动IC、LED驱动IC等领域均有着广泛的应用。介绍了典型的可集成功率高压器件，包括不同电压等级的横向双扩散金属氧化物半导体场效应晶体管（LDMOS）以及基于硅和SOI材料的横向绝缘栅双极型晶体管（LIGBT），此外还介绍了高低压器件集成的BCD工艺和其他的功率集成关键技术，包括隔离技术、高压互连技术、dV/dt技术、di/dt技术、抗闩锁技术等，最后讨论了功率集成器件及其兼容技术的发展趋势。

关键词: 功率集成器件, 横向双扩散金属氧化物半导体场效应晶体管, 横向绝缘栅双极型晶体管, BCD工艺, 兼容技术

Abstract: Integrated power devices are widely used in AC/DC power conversion ICs, high-voltage gate driver ICs, LED driver ICs and other fields. This article introduces typical integrated high-voltage power devices, including lateral double-diffusion MOSFET (LDMOS) of different voltage levels and lateral insulated gate bipolar transistor (LIGBT) based on silicon and SOI. In addition, it also introduces the BCD process of high and low voltage device integration and other key power integration technologies, including isolation technology, high voltage interconnection technology, dV/dt technology, di/dt technology, anti-latch-up technology, etc., and finally the development trend of integrated power devices and compatible technologies are discussed.

Key words: integratedpowerdevice, lateraldouble-diffusionMOSFET, lateralinsulatedgatebipolartransistor, BCDprocess, compatibletechnology

中图分类号:

乔明;袁柳. 功率集成器件及其兼容技术的发展^*[J]. 电子与封装, 2021, 21(4): 040405 .

QIAO Ming, YUAN Liu. Development of Integrated Power Devices and Compatible Technologies[J]. Electronics & Packaging, 2021, 21(4): 040405 .

参考文献

[1] DISNEY D, LETAVIC T, TRAJKOVIC T, et al. High-voltage integrated circuits: history, state of the art, and future prospects[J]. IEEE Transactions on Electron Devices, 2017, 64(3):659-673.
[2] CHEN Y, CHANG C, YANG P. A novel constant current control circuit for a primary-side controlled AC-DC LED driver[C]. International Conference on Electronics, Computer and Computation, 2014:1-4.
[3] MATSUDAI T, SATO K, YASUHARA N, et al. 0.13 μm CMOS/DMOS platform technology with novel 8 V/9 V LDMOS for low voltage high-frequency DC-DC converters[C]. IEEE International Symposium on Power Semiconductor Devices and ICs. 2010:315-318.
[4] TARUI Y. Diffusion self-aligned enhance-depletion MOS-IC (DSA-ED-MOS-IC)[J]. Solid State Devices, 1970:193-198.
[5] QIAO M, LI Y, ZHOU X, et al. A 700-V junction-isolated triple RESURF LDMOS with N-type top layer[J]. IEEE Electron Device Letters, 2014, 35(7):774-776.
[6] ZHANG W T, QIAO M, WU L, et al. Ultra-low specific on-resistance SOI high voltage trench LDMOS with dielectric field enhancement based on ENBULF concept[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2013:329-332.
[7] QIAO M, YU Y, ZHANG W T, et al. Lateral high-voltage device: US10068965B1[P]. 2018-09-04.
[8] JUENGLING W, HILLENIUS S J, CHEN M L, et al. Integration of poly buffered LOCOS and gate processing for submicrometer isolation technique[J]. IEEE Transactions on Electron Devices, 2002, 38(12):2721.
[9] CHOI Y, JEON C, KIM M. Design and process considerations for 1200 V HVIC technology[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2009:311-314.
[10] QIAO M, WANG Y, LI Y, et al. Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer[J]. Superlattices and Microstructures, 2014, 75:796-805.
[11] OKAWA T, EGUCHI H, TAKI M, et al. 2000 V SOI LDMOS with new drift structure for HVICs[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2016:435-438.
[12] APPELS J A, VAES H M J. High voltage thin layer devices (RESURF devices)[C]. IEEE International Electron Devices Meeting, 1979:238-241.
[13] IMAM M, QUDDUS M, ADAMS J, et al. Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices[J]. IEEE Transactions on Electron Devices, 2004, 51(1):141-148.
[14] 王宏杰, 蔡曦, 乔明,等. PDP驱动电路中高压NLDMOS设计[C]. 全国半导体集成电路,硅材料学术会议. 2007:828-830.
[15] HUANG Y, QIAO M, SUN Z, et al. 230 V SOI PLDMOS with gate field plate for PDP scan IC[C]. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2012:1-3.
[16] LUDIKHUIZE A W. A review of RESURF technology[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2000:11-18.
[17] 方健, 张正璠, 雷宇,等. 有n埋层结构的1200V横向变掺杂双RESURF LDMOS研制[J]. 半导体学报, 2005, 26(3):541-546.
[18] IMAM M, HOSSAIN Z, QUDDUS M, et al. Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process[J]. IEEE Transactions on Electron Devices, 2003, 50(7):1697-1700.
[19] DESOUZA M M, NARAYANAN E M S. Double resurf technology for HVICs[J]. Electronics Letters, 1996, 32(12):1092.
[20] QIAO M, WANG Z K, WANG Y R, et al. 3-D edge termination design and ron’s-BV model of a 700-V triple RESURF LDMOS with N-type top layer[J]. IEEE Transactions on Electron Devices, 2017, 64(6):2579-2586.
[21] QIAO M, WANG Y, ZHOU X, et al. Analytical modeling for a novel triple RESURF LDMOS with N-top Layer[J]. IEEE Transactions on Electron Devices, 2015, 62(9):2933-2939.
[22] QIAO M, YU L L, WANG H H, et al. On the progressive performance of a 700-V triple RESURF LDMOS based on substrate termination technology[C]. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2016:385-388.
[23] WASISTO H S, SHEU G, YANG S M, et al. A novel 800 V multiple RESURF LDMOS utilizing linear p-top rings[C]. IEEE Region 10 Conference, 2010:75-79.
[24] SAMEH K. Multiple lateral RESURF LDMOST: US8106451B2[P]. 2012-01-31.
[25] UDREA F, POPESCU A. 3D RESURF double-gate MOSFET: a revolutionary power device concept[J]. Electronics Letters, 1998, 34(8):808-809.
[26] QIAO M, HU X, WEN H, et al. A novel substrate-assisted RESURF technology for small curvature radius junction[C]. IEEE International Symposium on Power Semiconductor Devices and ICs. IEEE, 2011:16-19.
[27] QIAO M, WU W, ZHANG B, et al. A novel substrate termination technology for lateral double-diffused MOSFET based on curved junction extension[J]. Semiconductor Science and Technology, 2014, 29(4):045002.
[28] GROVE A S, JR O L, HOOPER W W. Effect of surface fields on the breakdown voltage of planar silicon p-n junctions[J]. IEEE Transactions on Electron Devices, 1967, 14(3):157-162.
[29] BRIEGER K P, FALCK E. The contour of an optimal field plate-an analytical approach[J]. IEEE Transactions on Electron Devices, 1988, 35(5):684-688.
[30] BASSUS R C, FALCK E, GERLACH W. Application of the evolution strategy to optimize multistep field plates for high voltage planar pn-junctions[J]. Archiv Fur Elektrotechnik, 1992, 75(5):345-349.
[31] HE Y T, QIAO M, LI L, et al. A Lateral regulator diode with field plates for light-emitting-diode lighting[J]. Chinese Physics Letters, 2016, 33(9):97-101.
[32] CHEN X B, ZHANG B, LI Z J. Theory of optimum design of reverse-biased p-n junctions using resistive field plates and variation lateral doping[J]. Solid-State Electronics, 1992, 35(9):1365-1370.
[33] QIAO M, ZHUANG X, WU L J. Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates[J]. Chinese Physics B, 2012, 21(10):504-511.
[34] QIAO M, LI C, LIU Y, et al. Design of a novel triple reduced surface field LDMOS with partial linear variable doping n-type top layer[J]. Superlattices and Microstructures, 2016, 93:242-247.
[35] LORENZ L, DEBOY G, KNAPP A, et al. COOLMOS/sup TM/-a new milestone in high voltage power MOS[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1999:3-10.
[36] CHEN X B, JOHNNY S. Optimization of the specific on-resistance of the COOLMOS[J]. IEEE Transactions on Electron Devices, 2001, 48(2):344-348.
[37] ZHANG W, ZHANG B, QIAO M, et al. The RON, min of balanced symmetric vertical super junction based on R-well model[J]. IEEE Transactions on Electron Devices, 2016, 64(1):224-230.
[38] ZHANG W T, PU S, LAI C L, et al. Non-full depletion mode and its experimental realization of the lateral superjunction[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2018:475-478.
[39] DARWISH M, BOARD K. Lateral resurfed COMFET[J]. Electronics Letters, 1984, 20(12):519-520.
[40] FU Q, ZHANG B, QIAO M, et al. Reverse conducting lateral insulated-gate bipolar transistors with a non-local band-to-band tunnelling junction[J]. Micro and Nano Letters, 2014, 9(8):544-547.
[41] MAO K, QIAO M, ZHANG B, et al. A 800 V dual conduction paths segmented anode LIGBT with low specific on-resistance and small shift voltage[J]. Journal of Semiconductors, 2014, 35(005):36-41.
[42] YASUHARA N, FUNAKI H, MATSUDAI T, et al. Experimental verification of large current capability of lateral IEGTs on SOI[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1996:97-100.
[43] SAKANO J, SHIRAKAWA S, HARA K, et al. Large current capability 270 V lateral IGBT with multi-emitter[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2010:83-86.
[44] DUAN S L, QIAO M, MAO K, et al. 700 V segmented anode LIGBT with low on-resistance and onset voltage[C]. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010:897-899.
[45] GOUGH P A, SIMPSON M R, RUMENNIK V. Fast switching lateral insulated gate transistor[C]. IEEE International Electron Devices Meeting, 1986:218-221.
[46] UDREA F, UDUGAMPOLA U N K, SHENG K, et al. Experimental demonstration of an ultra-fast double gate inversion layer emitter transistor (DG-ILET)[J]. IEEE Electron Device Letters, 2002, 23(12):725-727.
[47] CHEN W, ZHANG B, LI Z. Area-efficient fast-speed lateral IGBT with a 3-D n-region-controlled anode[C]. IEEE Electron Device Letters, 2010, 31(5): 467-469.
[48] ZHU J, ZHANG L, SUN W, et al. Electrical Characteristic Study of an SOI-LIGBT With Segmented Trenches in the Anode Region[J]. IEEE Transactions on Electron Devices, 2016, 63(5):2003-2008.
[49] HE Y T, QIAO M, ZHANG B, et al. A novel low turnoff loss carrier stored SOI LIGBT with trench gate barrier[J]. Superlattices and Microstructures, 2016, 89:179-187.
[50] JIANG L L, FAN H, QIAO M, et al. ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications[J]. Microelectronics Reliability, 2013:687-693.
[51] CAI J, SIN J K O, MOK P K T, et al. A new lateral trench-gate conductivity modulated power transistor[J]. IEEE Transactions on Electron Devices, 1999, 46(8):1788-1793.
[52] LU, D. H, JIMBO, S, FUJISHIMA, N. A low on-resistance high voltage soi ligbt with oxide trench in drift region and hole bypass gate configuration[C]. IEEE International Electron Devices Meeting, 2005:381-384.
[53] KRISHNA S, KUO J, GAETA I S. An analog technology integrates bipolar, CMOS, and high-voltage DMOS transistors[J]. IEEE Transactions on Electron Devices, 1984, 31(1):89-95.
[54] ANDREINI, A, CONTIERO, GALBIATI P. A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts[J]. IEEE Transactions on Electron Devices, 1986, 33(12):2025-2030.
[55] CONTIERO C, ANDREINI A, GALBIATI P. Roadmap differentiation and emerging trends in BCD technology[C]. IEEE European Solid-State Device Research Conference, 2005:275-282.
[56] QIAO M, PU S, ZHANG B, et al. Bipolar-CMOS-DMOS semiconductor device and manufacturing method: US10607987B2[P]. 2020-03-31.
[57] QIAO M, LAI C L, HE L R, et al. BCD semiconductor device and method for manufacturing the same: US10510747B1[P]. 2019-10-17.
[58] QIAO M, JIANG L L, ZHANG B, et al. A 700 V BCD technology platform for high voltage applications[J]. Journal of Semiconductors, 2012, 33(4):47-50.
[59] VENTURATO M, CANTONE G, RONCHI F, et al. A novel 0.35 μm 800 V BCD technology platform for offline applications[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2012:397-400.
[60] LUDIKHUIZE A W. A versatile 700-1200-V IC process for analog and switching applications[J]. IEEE Transactions on Electron Devices, 1991, 38(7):1582-1589.
[61] WANG H, QIAO M, JIN F, et al. A 0.35 μm 600 V ultra-thin epitaxial BCD technology for high voltage gate driver IC[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2018:311-314.
[62] ST Microelectronics. Innovation & technology: BCD [EB/OL]. [2019-5-1]. https://www.st.com/content/st_com/en/about/innovation---technology/BCD.html.
[63] MAO K, QIAO M, JIANG L L, et al. A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2013:397-400.
[64] 乔明, 方健, 肖志强,等. 1200 V MR D-RESURF LDMOS与BCD兼容工艺研究[J]. 半导体学报, 2006, 27(8):1447-1452.
[65] CHENG S K, FANG D, QIAO M, et al. A novel 700 V deep trench isolated double RESURF LDMOS with P-sink layer[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2017:323-326.
[66] QIAO M, ZHANG K, ZHOU X, et al. 250 V thin-layer SOI technology with field pLDMOS for high-voltage switching IC[J]. IEEE Transactions on Electron Devices, 2015, 62(6):1910-1976.
[67] QIAO M, LUO B, HU X I, et al. SOI devices for plasma display panel driver chip: US8704329B2 [P]. 2014-4-22.
[68] QIAO M, ZHOU X, HE Y, et al. 300-V high-side thin-layer-SOI field pLDMOS with multiple field plates based on field implant technology[J]. IEEE Electron Device Letters, 2012, 33(10):1438-1440.
[69] QIAO M, ZHANG X, WEN S, et al. A review of HVI technology[J]. Microelectronics Reliability, 2014, 54(12):2704-2716.
[70] 乔明, 周贤达, 段明伟，等. 具有高压互连线的多区双RESURF LDMOS击穿特性[J]. 半导体学报, 2007, 9:1428-1432.
[71] FUJISHIMA N, TAKEDA H. A novel field plate structure under high voltage interconnections[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1990:91-96.
[72] SAKURAI N, NEMOTO M, ARAKAWA H, et al. A three-phase inverter IC for AC220 V with a drastically small chip size and highly intelligent functions[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2002:310-315.
[73] 乔明, 张昕, 马金荣,等. 一种多片式高压驱动电路: ZL201410450116.5[P]. 2015-02-04
[74] FLACK E, GERLACH W. Influence of interconnections onto the breakdown voltage of planar high-voltage p-n junctions[J]. IEEE Transactions on Electron Devices, 1993, 40(2):439-447.
[75] QIAO M, LI Z, ZHANG B, et al. Realization of over 650 V double RESURF LDMOS with HVI for high side gate drive IC[C]. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2006:248-250.
[76] DESOUZA M M, NARAYANAN E M S. Double resurf technology for HVICs[J]. Electronics Letters, 1996, 32(12):1092.
[77] 文帅, 乔明. 具有单层浮空场板的高压LDMOS器件研究[J]. 电子与封装, 2015, 15(8):34-37.
[78] TERASHIMA T, YOSHIZAWA M, FUKUNAGA M, et al. Structure of 600 V IC and a new voltage sensing device[J]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1993: 224-229.
[79] MCARTHUR D C, MULLEN R A. High voltage MOS transistor having shielded crossover path for a high voltage connection bus: US5040045[P]. 1991-8-13.
[80] TERASHIMA T. Structure for preventing electric field concentration in semiconductor device: US5270568[P]. 1993-12-14.
[81] TERASHIMA T, YAMASHITA J, YAMADA T. Over 1000 V n-ch LDMOSFET and p-ch LIGBT with JI RESURF structure and multiple floating field plate[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1995:455-459.
[82] SHIMIZU K, RITTAKU S, MORITANI J. A 600 V HVIC process with a built-in EPROM which enables new concept gate driving[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2004:379-382.
[83] ENDO K, BABA Y, UDO Y, et al. A 500 V 1 A 1-chip inverter IC with a new electric field reduction structure[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1994:379-383.
[84] MURRAY A F J, LANE W A. Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates[J]. IEEE Transactions on Electron Devices, 1997, 44(1):185-189.
[85] FUJIHIRA T, YANO Y, OBINATA S, et al. Self-shielding: new high-voltage inter-connection technique for HVICs[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1996:231-234.
[86] FUJIHIRA T, YANO Y, OBINATA S, et al. High voltage integrated circuit, high voltage junction terminating structure, and high voltage MIS transistor: US6124628[P]. 2000-9-26.
[87] KIM S L, JEON C K, KIM M H, et al. Realization of robust 600 V high side gate drive IC with a new isolated self-shielding structure[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2005:143-146.
[88] KIM S L, JEON C K, KIM M S, et al. 1200 V interconnection technique with isolated self-shielding structure[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2006:1 - 4.
[89] 乔明, 方健, 李肇基,等. 基于耦合式电平位移结构的高压集成电路[J].半导体学报, 2006, 27(11):2040-2045.
[90] GROEGER J, SCHINDLER A, WICHT B, et al. Optimized dv/dt, di/dt sensing for a digitally controlled slope shaping gate driver[C]. IEEE Applied Power Electronics Conference and Exposition, 2017:3564-3569.
[91] PARK S, JAHNS T M. Flexible dv/dt and di/dt control method for insulated gate power switches[C]. IEEE Industry Applications Conference, 2003:657-664.
[92] SHU L, ZHANG J M, PENG F Z, et al. Active current source IGBT gate drive with closed-loop di/dt and dv/dt control[J]. IEEE Transactions on Power Electronics, 2017, 32(5):3787-3796.
[93] SAWEZYN H. Lowering the drawbacks of slowing down di/dt and dv/dt of insulated gate transistors[C]. International Conference on Power Electronics Machines and Drives, 2002:551-556.
[94] CHEN W, LIU C, SHI Y, et al. Design and characterization of high di/dt CS-MCT for pulse power applications[J]. IEEE Transactions on Electron Devices, 2017, 64(10):4206-4212.
[95] DAI C T, KER M D. Investigation of unexpected latchup path between HV-LDMOS and LV-CMOS in a 0.25- μm 60-V/5-V BCD technology[J]. IEEE Transactions on Electron Devices, 2017, 64(8):3519-3523.
[96] BUCCELLA P, STEFANUCCI C, SALLESE J M, et al. Active guard ring characterization for smart power ICs[C]. IEEE International Conference Mixed Design of Integrated Circuits and Systems, 2016:305-309.
[97] LEE J H, CHEN S H, TSAI Y T, et al. The influence of NBL layout and LOCOS space on component ESD and system level ESD for HV-LDMOS[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2007:173-176.
[98] WANG L, WANG J, LI R, et al. Novel STI scheme and layout design to suppress the kink effect in LDMOS transistors[J]. Semiconductor Science and Technology, 2008, 23(7):075025.
[99] QI Z, QIAO M, LIANG L F, et al. High trigger current NPN transistor with excellent double-snapback performance for high-voltage output ESD protection[J]. IEEE Electron Device Letters, 2020, 41(3):453-456.
[100] QI Z, QIAO M, LIANG L F, et al. Novel silicon-controlled rectifier with snapback-free performance for high-voltage and robust ESD protection[J]. IEEE Electron Device Letters, 2019, 40(3):435-438.
[101] KNIFFIN, M.L, THOMA, R, VICTORY, J. Physical compact modeling of layout dependent metal resistance in integrated LDMOS power devices[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2000:173-176.
[102] QIAO M, WANG Z, WANG H, et al. Edge termination design of a 700-V triple RESURF LDMOS with n-type top layer[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2017:319-322.
[103] 乔明,肖倩倩,余洋,等. 横向高压功率器件的结终端结构: ZL201610728940.1[P]. 2019-09-27.
[104] 乔明, 何林蓉, 童成伟,等. 一种抗闩锁版图结构: ZL201910844970.2[P]. 2019-12-03.
[105] KOISHIKAWA Y. Enhancement of breakdown voltage in MOSFET semiconductor device: US5633521[P]. 1997-05-27.
[106] HUANG A Q, SUN N X, ZHANG B, et al. Low voltage power devices for future VRM[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 1998:395-398.
[107] HSHIEH F I, KOON C S, TSUI Y M. Tsui, trench MOSFET with structure having low gate charge: US6472708B1[P]. 2002-10-29.
[108] CALAFUT D S. Power MOS device with improved gate charge performance: US6534825B2[P]. 2003-3-18.
[109] QIAO M, WANG Z K, FANG D. et al. Split-gate enhanced power MOS device. US10720524B1[P].2020-07-21.
[110] QIAO M, WANG Z K, WANG R D. et al. Power semiconductor devices: US10608106B2[P]. 2020-3-31.
[111] SAITO W, NITTA T, KAKIUCHI Y, et al. Suppression of dynamic on-resistance increase and gate charge measurements in high-voltage GaN-HEMTs with optimized field-plate structure[J]. IEEE Transactions on Electron Devices, 2007, 54(8):1825-1830.
[112] SAXENA R S, KUMAR M J. Polysilicon spacer gate technique to reduce gate charge of a trench power MOSFET[J]. IEEE Transactions on Electron Devices, 2012, 59(3):738-744.
[113] PETRUZZELLO J, LETAVIC T J, SIMPSON M. SOI LDMOS structure with improved switching characteristics: US6468878B1[P]. 2002-10-22.
[114] QIAO M, LIANG L, ZU J, et al. A review of high-voltage integrated power device for AC/DC switching application[J]. Microelectronic Engineering, 2020, 232:111416.
[115] ZHOU X, YUAN Z Y, DENG X, et al. Investigation on 4H SiC MOSFET with three-section edge termination[J]. Superlattices and Microstructures, 2018, 124:139-144.
[116] HE Y T, QIAO M, WANG Z, et al. A low turnoff loss SOI LIGBT with p-buried layer and double gates[C]. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2016:1092-1094.
[117] QIAO M, ZHANG B, LI Z J, et al. Analysis of the back-gate effect on the breakdown behavior of lateral high-voltage SOI transistors[J]. Acta Physica Sinica, 2007, 56(7):3990-3995.
[118] LIM H T, UDREA F, GARNER D M, et al. Modelling of self-heating effect in thin SOI and Partial SOI LDMOS power devices[J]. Solid State Electronics, 1999, 43(7):1267-1280.
[119] UDREA F, POPESCU A, MILNE W. Breakdown analysis in JI, SOI and partial SOI power structures[C]. IEEE International SOI Conference, 1997:102-103.
[120] TADIKONDA R, HARDIKAR S, NARAYANAN E M S. Realizing high breakdown voltages (>600 V) in partial SOI technology[J]. Solid State Electronics, 2004, 48(9):1655-1660.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

功率集成器件及其兼容技术的发展^*

Development of Integrated Power Devices and Compatible Technologies

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 2

编辑推荐

Metrics

本文评价

[1]	蒋红利, 江月艳, 孙志欣, 邵卓, 钟涛, 高欣宇. 一种高压驱动器的抗辐射加固设计[J]. 电子与封装, 2023, 23(8): 80303-.
[2]	周淼, 汤亮, 何逸涛, 陈辰, 周锌. 一种部分超结型薄层SOI LIGBT器件的研究^*[J]. 电子与封装, 2022, 22(9): 90403-.