时钟恢复系统研究与实现*

doi:10.16257/j.cnki.1681-1070.2025.0090

电子与封装 ›› 2025, Vol. 25 ›› Issue (9): 090301 . doi: 10.16257/j.cnki.1681-1070.2025.0090

时钟恢复系统研究与实现^*

鲍宜鹏^1,2，苗韵^1,2，杨晓刚^1,2，傅建军^1,2

1. 中科芯集成电路有限公司，江苏无锡 214072；2. 智能汽车安全技术全国重点实验室，江苏无锡 214072

出版日期:2025-09-28 发布日期:2025-09-28
作者简介:鲍宜鹏（1985—），男，江苏宿迁人，硕士，高级工程师，主要研究方向为SoC设计方法学。

Research and Implementation of Clock Recovery System

BAO Yipeng^1,2, MIAO Yun^1,2, YANG Xiaogang^1,2, FU Jianjun^1,2

1. China Key System & Integrated Circuit Co., Ltd., Wuxi 214072, China; 2. State Key Laboratory of Intelligent Vehicle Safety Technology, Wuxi 214702, China

Online:2025-09-28 Published:2025-09-28

摘要/Abstract

摘要： 时钟设计是芯片设计中的关键环节之一。芯片的系统时钟设计必须考虑外部环境的影响，还应考虑电路的复杂性与成本。通过对时钟恢复系统（CRS）实现方法及其特性的综述，指出现有CRS设计存在的不足。结合芯片内置的振荡器特性，采用全数字电路的设计方法，设计并实现一种时钟恢复系统，该电路结构简单、成本低，在通信和无线电系统等领域具有广泛的应用前景。

关键词: 时钟恢复系统；全数字电路；振荡器

Abstract: Clock design is one of the critical aspects of chip design. The system clock design of the chip must consider external environmental factors, as well as the complexity and cost of the circuits. By summarizing the implementation methods and characteristics of the clock recovery system (CRS), the design shortcomings of existing CRSs are identified. By combining the characteristics of the chip’s built-in oscillator, a full-digital circuit design method is proposed to implement a clock recovery system. This circuit features a simple structure and low cost, offering broad application prospects in fields such as communications and radio systems.

Key words: clock recovery system; full-digital circuit; oscillator

中图分类号:

TN402
TN47

鲍宜鹏，苗韵，杨晓刚，傅建军. 时钟恢复系统研究与实现^*[J]. 电子与封装, 2025, 25(9): 090301 .

BAO Yipeng, MIAO Yun, YANG Xiaogang, FU Jianjun. Research and Implementation of Clock Recovery System[J]. Electronics & Packaging, 2025, 25(9): 090301 .

参考文献

[1] 朱良辰, 胡越黎, 冉峰. 一种MCU时钟系统的设计[J]. 电子技术应用, 2003, 29(9): 75-78.
[2] 朱全庆, 李海华, 邹雪城, 等. 一种快速以太网卡芯片时钟恢复电路[J]. 固体电子学研究与进展, 2004, 24(4): 472-475.
[3] 朱彬. USB中高速全数字时钟恢复电路的设计[D]. 南京：东南大学, 2009.
[4] ANAND S B, RAZAVI B. A CMOS clock recovery circuit for 2.5-Gb/s NRZ data[J]. IEEE Journal of Solid-State Circuits, 2001, 36(3): 432-439.
[5] ZHANG R Y. Clock and data recovery circuits[D]. Pullman: Washington State University, 2004.
[6] HSU T Y, SHIEH B J, LEE C Y. An all-digital phase-locked loop (ADPLL)-based clock recovery circuit[J]. IEEE Journal of Solid-State Circuits, 1999, 34(8): 1063-1073.
[7] SONNTAG J L, STONICK J. A digital clock and data recovery architecture for multi-gigabit/s binary links[J]. IEEE Journal of Solid-State Circuits, 2006, 41(8): 1867-1875.
[8] VAUCHER C S, FRAMBACH J P, VAN DER TANG J D. High-speed architectures and building blocks for clock and data recovery systems[J]. International Journal of High Speed Electronics and Systems, 2005, 15(3): 581-597.
[9] COBAN A L, KOROGLU M H, AHMED K A. A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs[J]. IEEE Journal of Solid-State Circuits, 2005, 40(9): 1940-1947.
[10] ZHANG R, LA RUE G S. Fast acquisition clock and data recovery circuit with low jitter[J]. IEEE Journal of Solid-State Circuits, 2006, 41(5): 1016-1024.
[11] MAILLARD X, DEVISCH F, KUIJK M. A 900-Mb/s CMOS data recovery DLL using half-frequency clock[J]. IEEE Journal of Solid-State Circuits, 2002, 37(6): 711-715.
[12] SIDIROPOULOS S, HOROWITZ M A. A semidigital dual delay-locked loop[J]. IEEE Journal of Solid-State Circuits, 1997, 32(11): 1683-1692.
[13] 鲍宜鹏, 史兴强, 杨晓刚, 等. 一种时钟恢复系统电路: ZL202110886706.2[P]. 2021-10-06.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

时钟恢复系统研究与实现^*

Research and Implementation of Clock Recovery System

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 0

编辑推荐

Metrics

本文评价