关键词: 时钟校准, 延迟锁相环, 数模转换器, 占空比调制

Abstract: A 3.5 GHz clock calibration circuit of high speed and high precision DAC implemented in SMIC 65 nm CMOS is presented. The circuit includes a delay lock loop (DLL) to optimize the timing hand-off between the digital clock domain and the DAC core over temperature, time, and power supply variation, also to ensure correct data transfer with 3.5 GHz and improve the reliability of system clock. The proposed circuit is with 1.2 V/3.3 V dual power supply, 2 ps/LSB of the clock phase regulating precision, programmable target set-phase and the ability of clock duty cycle modulation. The largest power dissipation is lower than 60 mW.

Key words: clock calibration, delay lock loop, digital-to-analog converter, duty cycle modulation